Patent application number | Description | Published |
20130075688 | Semiconductor Memory Device and Manufacturing Method Thereof - A semiconductor memory device includes a first insulating portion. The semiconductor memory device further includes a phase-change material element that contacts the first insulating portion. The semiconductor memory device further includes an electrode that contacts a side surface of the phase-change material element, the side surface of the phase-change material element being not parallel to a top surface of the electrode. The semiconductor memory device further includes a second insulating portion surrounding the phase-change material element. | 03-28-2013 |
20130123391 | COPOLYMERS - Embodiments include copolymers obtainable by reacting styrenic compound, maleic anhydride, and a cyclo-olefin, wherein the cyclo-olefin is selected from the group consisting of dicyclopentadiene, dicyclopentadiene derivatives, norbornene, norbornene derivatives, and combinations thereof. Embodiments include curable compositions having the copolymer, an epoxy compound and a solvent. | 05-16-2013 |
20130145984 | METHOD OF EPITAXIAL GROWTH EFFECTIVELY PREVENTING AUTO-DOPING EFFECT - This invention relates to a method of epitaxial growth effectively preventing auto-doping effect. This method starts with the removal of impurities from the semiconductor substrate having heavily-doped buried layer region and from the inner wall of reaction chamber to be used. Then the semiconductor substrate is loaded in the cleaned reaction chamber to be pre-baked under vacuum conditions so as to remove moisture and oxide from the surface of said semiconductor substrate before the extraction of the dopant atoms desorbed from the surface of the semiconductor substrate. Next, under high temperature and low gas flow conditions, a first intrinsic epitaxial layer is formed on the surface of said semiconductor substrate where the dopant atoms have been extracted out. Following this, under low temperature and high gas flow conditions, a second epitaxial layer of required thickness is formed on the structural surface of the grown intrinsic epitaxial layer. Last, silicon wafer is unloaded after cooling. This method can prevent auto-doping effect during the epitaxial growth on semiconductor substrate and thus ensure the performance and enhance the reliability of the devices in peripheral circuit region. | 06-13-2013 |
20130189799 | METHOD OF FABRICATING DUAL TRENCH ISOLATED EPITAXIAL DIODE ARRAY - The present invention discloses a method of fabricating dual trench isolated epitaxial diode array. This method starts with the formation of heavily-doped first conductivity type regions and heavily-doped second conductivity type regions on the substrate, followed by epitaxial growth, then the formation of the isolations between diode array word lines by deep trench etch and the formation of the isolations between bit lines vertical to deep trenches by shallow trench etch, and finally the formation of separate diode array cells in the regions enclosed by deep and shallow trench isolations by ion implantation. This invention also provides a method of preventing the crosstalk current between adjacent word lines and bit lines of epitaxial diode arrays isolated by foregoing dual shallow trenches. This invention can be used for diode-driven, high-density, large-capacity memory, such as phase change random access memory, resistive memory, magnetic memory and ferroelectric memory; the method thereof is completely compatible with conventional complementary metal-oxide semiconductor (CMOS) process, and because the diode arrays can be formed before the formation of peripheral circuits, no drift of peripheral circuits will be caused by the thermal process thereof, thereby solving the technical challenge of fabricating high-density, large-capacity embedded phase change random access memory. | 07-25-2013 |
20140128545 | CURABLE COMPOSITIONS - Embodiments include curable compositions including an epoxy resin and a hardener component including a terpolymer having first constitutional unit, a second constitutional unit, and a third constitutional unit, where the epoxy group to the second constitutional unit has a molar ratio in a range of 1.0:1.0 to 2.7:1.0. Embodiments include prepregs that include a reinforcement component and the curable composition and an electrical laminate formed with the curable composition. | 05-08-2014 |
20140294115 | METHOD AND APPARATUS FOR CONFIGURING TRANSMISSION MODE - Embodiments of the present invention provide a method and an apparatus for configuring a transmission mode, where the method includes: obtaining channel matrix information, where the channel matrix information is any one of the following: a precoding matrix indicator which most matches a current uplink channel matrix of a terminal, a current downlink precoding matrix indicator of the terminal, an uplink channel matrix of the terminal and the precoding matrix indicator which most matches the current uplink channel matrix of the terminal, and the uplink channel matrix of the terminal and the current downlink precoding matrix indicator of the terminal; determining performance of data transmission performed by adopting a closed-loop mode and an open-loop mode according to the channel matrix information, and selecting the data transmission mode according to the determined performance of data transmission, where the data transmission mode includes the open-loop mode, the closed-loop mode. | 10-02-2014 |
20150102451 | NANOSCALE SILICON SCHOTTKY DIODE ARRAY FOR LOW POWER PHASE CHANGE MEMORY APPLICATION - Methods and devices associated with a phase change memory include Schottky diodes operating as selectors having a low turn-on voltage, low sneak current and high switching speed. A method of forming a semiconductor device includes providing a semiconductor substrate having a diode array region and a peripheral device region, forming an N+ buried layer in the diode array region, forming a semiconductor epitaxial layer on the N+ buried layer, and forming deep trench isolations through the epitaxial layer and the N+ buried layer along a first direction. The method also includes forming shallow trench isolations in the diode array region and in the peripheral region along a second line direction. The method also includes forming an N− doped region between the deep and shallow trench isolations and forming a metal silicide on a surface of the N− doped region. | 04-16-2015 |
20150102455 | METHOD OF FABRICATING DUAL TRENCH ISOLATED SELECTIVE EPITAXIAL DIODE ARRAY - Methods and devices associated with phase change memory include diodes operating as selector switches having a large driving current and high switching speed. A method of forming a semiconductor device includes providing a semiconductor substrate, defining a diode array region and a peripheral region on the semiconductor substrate, forming an N+ buried layer in the diode array region by performing an ion implantation process and an annealing process. The method also includes forming a semiconductor epitaxial layer on the N+ buried layer, forming deep trench isolations through the epitaxial layer and the N+ buried layer into a portion of the substrate in the first direction, and forming shallow trench isolations in the diode array region and in the peripheral region in the second direction. The shallow trench isolation has a depth equal to or greater than a thickness of the epitaxial layer. | 04-16-2015 |