| Patent application number | Description | Published |
|---|
| 20080217679 | MEMORY UNIT STRUCTURE AND OPERATION METHOD THEREOF - A memory unit is proposed. The memory unit includes a Si substrate, a trapping layer formed on the Si substrate, a first and a second doping regions formed in the Si substrate on either side of the trapping layer, a gate formed on the trapping layer, a first oxide layer formed between the gate and the trapping layer, a high-Dit material layer formed between the Si substrate and the trapping layer, and a second oxide layer formed between the high-Dit material layer and the trapping layer, wherein an interface trap density (Dit) between the high-Dit material layer and the Si substrate is in a rang from 10 | 09-11-2008 |
| 20080258204 | MEMORY STRUCTURE AND OPERATING METHOD THEREOF - A memory structure including a substrate, a charge trapping layer, a block layer, a conducting layer and two doped regions is provided in the present invention. The charge trapping layer is disposed on the substrate. The block layer is disposed on the charge trapping layer. The conducting layer is disposed on the block layer. The doped regions are disposed respectively in the substrate on the two sides of the conducting layer. | 10-23-2008 |
| 20080266969 | METHOD OF OPERATING NON-VOLATILE MEMORY - A method of operating a non-volatile memory having a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain region is a data storage region. Before prosecuting the operation, electrons have been injected into the auxiliary charge region. When prosecuting the programming operation, a first voltage is applied to the gate, a second voltage is applied to the source region, a third voltage is applied to the drain region and a fourth voltage is applied to the substrate. The first voltage is greater than the fourth voltage, the third voltage is greater than the second voltage, and the second voltage is greater than the fourth voltage to initiate a channel initiated secondary hot electron injection to inject electrons into the data storage region. | 10-30-2008 |
| 20080304320 | MEMORY CELL AND METHOD OF PROGRAMMING THE SAME - A method of programming a memory cell is described. The memory cell includes a gate with a charge trapping layer isolated from a substrate for storing data with a first region and a second region separated from the first region. The method of programming the memory cell includes applying a first voltage arrangement with a first gate voltage for programming the first region and applying a second voltage arrangement with a second gate voltage for programming the second region. The first gate voltage is greater than the second gate voltage. | 12-11-2008 |
| 20080316810 | MEMORY UNIT - A memory unit is provided herein. Two non-volatile devices are used to store a logic state of the memory unit into the non-volatile devices. Although a power supply for the memory unit is shut down, the non-volatile devices still keep the data stored therein. The present invention not only has an advantage of high speed operation of a static random access memory (SRAM), but also has a function for storing data of a non-volatile memory. | 12-25-2008 |
| 20090207658 | OPERATING METHOD OF MEMORY DEVICE - An operating method of a memory array is provided. The operating method includes performing a programming operation. The programming operation is performed by applying a first voltage to a bit line of the memory array and a second voltage to a plurality of word lines of the memory array to cause simultaneously programming a plurality of selected memory cells in the memory array | 08-20-2009 |
| 20090296474 | PROGRAM AND ERASE METHODS WITH SUBSTRATE TRANSIENT HOT CARRIER INJECTIONS IN A NON-VOLATILE MEMORY - The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure. | 12-03-2009 |
| 20100074027 | HIGH SECOND BIT OPERATION WINDOW METHOD FOR VIRTUAL GROUND ARRAY WITH TWO-BIT MEMORY CELLS - A non-volatile VG memory array employing memory semiconductor cells capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in associating with at least one electrical insulating layer, such as an oxide, is disclosed. Bit lines of the memory array are capable of transmitting positive voltage to reach the source/drain regions of the memory cells of the array. A method that includes the hole injection erasure of the memory cells of the array that lowers the voltage threshold of the memory cells to a value lower than the initial voltage threshold of the cells is disclosed. The hole injection induced lower voltage threshold reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened. The programming and read steps reduce leakage current of the memory cells in the array. | 03-25-2010 |
| 20100090268 | SEMICONDUCTOR DEVICE AND MEMORY - A memory applicable to an embedded memory is provided. The memory includes a substrate, a gate, a charge-trapping gate dielectric layer, a source, and a drain. The gate is disposed above the substrate. The charge-trapping gate dielectric layer is disposed between the gate and the substrate. The source and the drain are disposed in the substrate beside the gate respectively. | 04-15-2010 |
| 20100135086 | METHOD OF OPERATING NON-VOLATILE MEMORY CELL AND MEMORY DEVICE UTILIZING THE METHOD - A method of operating a non-volatile memory cell is described, including pre-erasing the cell through double-side biased (DSB) injection of a first type of carrier and programming the cell through Fowler-Nordheim (FN) tunneling of a second type of carrier. | 06-03-2010 |
| 20100304541 | SYSTEMS AND METHODS FOR MEMORY STRUCTURE COMPRISING A PPROM AND AN EMBEDDED FLASH MEMORY - A memory structure that combines embedded flash memory and PPROM. The PPROM can be used as a memory structure. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. The PPROM cells are stacked on top of the flash memory cells and the PPROM density can be increased by implementing three-dimensional PPROM structures. | 12-02-2010 |
| 20100328996 | PHASE CHANGE MEMORY HAVING ONE OR MORE NON-CONSTANT DOPING PROFILES - A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions. | 12-30-2010 |
| 20110002166 | TWO-BIT NON-VOLATILE FLASH MEMORY ARRAY - A memory array comprises a semiconductor substrate, two-bit memory cells, word lines, a gate voltage source, bit lines and bit line control cells. The memory cells have a first and a second source/drain regions, each memory cell includes a dielectric trapping layer, and the dielectric trapping layer is disposed between a first oxide layer and a gate layer. The word lines are coupled to the gate layer. The gate voltage source is coupled to the word lines and configured to apply erase voltages between 14 and 20 volts to the word lines. The bit lines are in electrical communication with the first and the second source/drain regions. The bit line control cells are disposed at the beginning and end of each bit line, the bit line control cells are configured to control the electrical communication of each bit line with the first and the second source/drain regions. | 01-06-2011 |
| 20110116317 | PROGRAM AND ERASE METHODS WITH SUBSTRATE TRANSIENT HOT CARRIER INJECTIONS IN A NON-VOLATILE MEMORY - The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure. | 05-19-2011 |
