Chao-I Wu
Chao-I Wu, Tainan City TW
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20090101966 | Method of identifying logical information in a programming and erasing cell by on-side reading scheme - A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme. | 04-23-2009 |
20100290293 | METHOD OF IDENTIFYING LOGICAL INFORMATION IN A PROGRAMMING AND ERASING CELL BY ON-SIDE READING SCHEME - A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme. | 11-18-2010 |
Chao-I Wu, Tainan TW
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20090103363 | APPARATUS AND ASSOCIATED METHOD FOR MAKING A VIRTUAL GROUND ARRAY STRUCTURE THAT USES INVERSION BIT LINES - A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging. | 04-23-2009 |
20090323428 | METHOD FOR IMPROVING MEMORY DEVICE CYCLING ENDURANCE BY PROVIDING ADDITIONAL PULSES - A method for programming and erasing a PHINES memory device is comprising providing one or more additional pulses that are associated with a program or erase pulse, wherein the additional pulses are of similar polarity, but of lesser magnitude than the program or erase pulses. For an erase pulse on a PHINES memory device, two additional pulses can be utilized. For a program pulse on the source-side of a PHINES memory device, one additional pulse can be utilized that comprises a negative bias measured from a gate of the memory device to a source of the memory device. For a program pulse on the drain-side of a PHINES memory device, one additional pulse can be utilized that comprises a negative bias measured from a gate of the memory device to a drain of the memory device. | 12-31-2009 |
20100009504 | SYSTEMS AND METHODS FOR A HIGH DENSITY, COMPACT MEMORY ARRAY - A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array. | 01-14-2010 |
20100193858 | NAND MEMORY DEVICE WITH INVERSION BIT LINES AND METHODS FOR MAKING THE SAME - A NAND based memory device uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities in smaller packaging. In another aspect, a method for fabricating a NAND based memory device that uses inversion bit lines is disclosed. | 08-05-2010 |
20100221851 | TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING - A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure. | 09-02-2010 |
Chao-I Wu, Hsinchu County TW
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20080251831 | Semiconductor structure and process for reducing the second bit effect of a memory device - A non-volatile memory cell capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in association with at least one electrical dielectric layer, such as an oxide, with a P-type substrate and an N-type channel implanted in the well region of the substrate between two source/drain regions is disclosed. The N-type channel achieves an inversion layer without the application of bias voltage to the gate of the memory cell. A method that implants the N-type channel in the P-type substrate of the cell wherein the N-type channel lowers the un-programmed or programmed voltage threshold of the memory cell to a value lower than would exist without the N-type channel is disclosed. The N-type channel reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened. | 10-16-2008 |
20080304318 | MULTI-LEVEL-CELL TRAPPING DRAM - A memory device having at least one multi-level memory cell is disclosed, and each multi-level memory cell configured to store n multiple bits, where n is an integer, wherein the multiple bits are stored in a charge storage layer trapping charge carriers injected by application of a voltage to set or reset a threshold voltage V | 12-11-2008 |
Chao-I Wu, Jhubei City TW
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20120120723 | Dynamic Pulse Operation for Phase Change Memory - The control circuit performs a reset operation and a set operation that change the resistance states of phase change memory cells of the array. The control circuit changes at least one parameter, of at least one of the reset operation and the set operation for future operations. This change is responsive to an indicator of degraded memory state retention of the array. | 05-17-2012 |
Chao-I Wu, Hsin-Chu TW
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20140153326 | CELL SENSING CIRCUIT FOR PHASE CHANGE MEMORY AND METHODS THEREOF - A cell sensing circuit for a phase changing memory and methods thereof are provided. A specific one of the proposed methods includes: providing a sensing circuit having a sense amplifier, and two identical stable currents respectively received by a reference cell and a target cell; establishing a cell voltage on a cell side and a reference voltage on a reference side respectively via the two identical stable currents; and using the sense amplifier to determine a logic state of the target cell based on a voltage difference between the reference voltage and the cell voltage. | 06-05-2014 |
Chao-I Wu, Hsinchu City TW
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20140376308 | PHASE CHANGE MEMORY, WRITING METHOD THEREOF AND READING METHOD THEREOF - A phase change memory (PCM), a writing method thereof and a reading method thereof are provided. The PCM has a plurality of memory cells. The writing method comprises the following steps. At least one stress pulse is applied for aging at least one of the memory cells. A starting pulse is applied to all of the memory cells of the PCM for decreasing a resistance of each memory cell. A detection pulse is applied to all of the memory cells of the PCM for detecting the resistance of each memory cell. A set pulse is applied to the aged memory cells. A reset pulse is applied to the non-aged memory cells. | 12-25-2014 |