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Chao, Hsinchu City
Benson Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120085747 | HEATER ASSEMBLY AND WAFER PROCESSING APPARATUS USING THE SAME - A heater assembly and a wafer processing apparatus using the same are provided. The heater assembly comprises a substrate, a heater, a reflector and a protective layer. The substrate has a top surface, a side surface surrounding the top surface and a trench formed on the top surface. The heater comprises a heater element accommodated within the trench and two electrodes respectively connecting two ends of the heater element and extending outside of the substrate. The reflector covers an inner surface of the trench. The protective layer covers the top surface, the side surface and the trench. | 04-12-2012 |
Chen Chun Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090308925 | Electronic data capturing system that simulates the functionality of physical electronic data capture - The present invention relates to an electronic data capturing system that simulates the functionality of a physical electronic data capture (EDC), wherein the electronic data capturing system comprises a card reader, a client-end computer, a remote server, which are being connected in the above sequence, wherein the remote server is for simulating the functionality of an electronic data capture, and provides an electronic data capturing interface for being accessed by a web-page accessing means installed in the client-end computer, in such a manner that a card reader controlling unit installed in the client-end computer controls the card reader to read the card information from the card, the card information read from the client-end computer is sent through the web-page accessing means to the remote server, and transmitted to an acquiring server so as to proceed authorization for the transaction record, and the authorization result is then sent back from the remote server through the web-page accessing means and transmitted back to a screen on the client-end computer so that the authorization result is identified. | 12-17-2009 |
Chien-Sheng Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100308447 | SEMICONDUCTOR DEVICE - A semiconductor device includes at least a die carried by a substrate, a plurality of bond pads disposed on the die, a plurality of conductive components, and a plurality of bond wires respectively connected between the plurality of bond pads and the plurality of conductive components. The plurality of bond pads respectively correspond to a plurality of signals, and include a first bond pad configured for transmitting/receiving a first signal and a second bond pad configured for transmitting/receiving a second signal. The plurality of conductive components include a first conductive component and a second conductive component. The first conductive component is bond-wired to the first bond pad, and the second conductive component is bond-wired to the second bond pad. The first conductive component and the second conductive component are separated by at least a third conductive component of the plurality of conductive components, and the first signal is asserted when the second signal is asserted. | 12-09-2010 |
Chih-Ming Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100052036 | MEMORY DEVICE AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE - A semiconductor device disposed on a substrate is provided. The semiconductor device includes two isolation structures, a first conductive layer, a charge trapping layer, a second conductive layer and a gate dielectric layer. The two isolation structures are disposed in the substrate to define an active area. The second conductive layer across the two isolation structures is disposed on the substrate. The first conductive layer is disposed between the two isolation structures and between the second conductive layer and the substrate. The second conductive layer electrically connects with the first conductive layer. The charge trapping layer is disposed on the substrate. The gate dielectric layer is disposed between the first conductive layer and the substrate. An interface between the two isolation structures and the first conductive layer is covered by the charge trapping layer to restrain the kink effect. | 03-04-2010 |
Chih-Ping Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110318898 | HARD MASK FOR THIN FILM RESISTOR MANUFACTURE - Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer. | 12-29-2011 |
Chih-Yao Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110049521 | ACTIVE DEVICE ARRAY MOTHER SUBSTRATE AND METHOD OF FABRICATING DISPLAY PANEL - An active device array mother substrate including a substrate, pixel arrays, and a polymer-stabilized alignment curing circuit is provided. The substrate has panel regions, a circuit region, a first cutting line, and a second cutting line. The first cutting line is disposed on the circuit region between an edge of the substrate and the second cutting line. The active devices of the pixel arrays have a semiconductor layer. The polymer-stabilized alignment curing circuit disposed on the circuit region includes curing pads disposed between the edge of the substrate and the first cutting line and curing lines having an upper conductive layer connected to the corresponding curing pads and the corresponding pixel array. The upper conductive layer is in the same layer as the source/drain conductor. Therefore, the curing lines are capable of preventing problems such as peeling, so as to keep the polymer-stabilized alignment curing circuit operating normally. | 03-03-2011 |
| 20110199562 | TRANSFLECTIVE PIXEL STRUCTURE - A transflective pixel structure including a reflective region and a transmittance region is provided. The pixel structure includes an active device, a covering layer, a reflective electrode layer, a reflective electrode pattern and a transparent electrode layer. The covering layer is disposed in the reflective region and the transmittance region and covers the active device, where the covering layer has a contact opening at least disposed in the transmittance region. The reflective electrode layer is disposed in the reflective region. The reflective electrode pattern is disposed within the contact opening and extends onto a top surface of the covering layer surrounding the contact opening. The transparent electrode layer is disposed on a surface of the covering layer in the transmittance region. The transparent electrode layer is electrically connected to the reflective electrode layer and the transparent electrode layer is electrically connected to the active device through the contact opening. | 08-18-2011 |
Chuen-Guang Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110059568 | METHOD FOR FABRICATING NANOSCALE THERMOELECTRIC DEVICE - The present invention discloses a method for fabricating a nanoscale thermoelectric device, which comprises steps: providing at least one template having a group of nanoscale pores; forming a substrate on the bottom of the template; injecting a molten semiconductor material into the nanoscale pores to form a group of semiconductor nanoscale wires; removing the substrate to obtain a semiconductor nanoscale wire array; and using metallic conductors to cascade at least two semiconductor nanoscale wire arrays to form a thermoelectric device having a higher thermoelectric conversion efficiency. | 03-10-2011 |
Chu-Li Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090114935 | Light emitting diode and process for fabricating the same - A light emitting diode (LED) is provided. The LED at least includes a substrate, a saw-toothed multilayer, a first type semiconductor layer, an active emitting layer and a second type semiconductor layer. In the LED, the saw-tooth multilayer is formed opposite the active emitting layer below the first type semiconductor layer by an auto-cloning photonic crystal process. Due to the presence of the saw-tooth multilayer on the substrate of the LED, the scattered light form a back of the active emitting layer can be reused by reflecting and recycling through the saw-tooth multilayer. Thus, all light is focused to radiate forward so as to improve the light extraction efficiency of the LED. Moreover, the saw-tooth multilayer does not peel off or be cracked after any high temperature process because the saw-tooth multilayer has the performance of releasing thermal stress and reducing elastic deformation between it and the substrate. | 05-07-2009 |
| 20090274883 | NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD FOR FORMING THE SAME - An initial substrate structure for forming a nitride semiconductor substrate is provided. The initial substrate structure includes a substrate, a patterned epitaxial layer, and a mask layer. The patterned epitaxial layer is located on the substrate and is formed by a plurality of pillars. The mask layer is located over the substrate and covers a part of the patterned epitaxial layer. The mask layer includes a plurality of sticks and there is a space between the sticks. The space exposes a portion of an upper surface of the patterned epitaxial layer. | 11-05-2009 |
| 20100090312 | Nitride semiconductor structure and method for manufacturing the same - A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer. | 04-15-2010 |
| 20100243987 | DEVICE OF LIGHT-EMITTING DIODE AND METHOD FOR FABRICATING THE SAME - A device of a light-emitting diode and a method for fabricating the same are provided. The LED device is made by forming a patterned epitaxial layer, a light-emitting structure, etc., on a substrate. In a subsequent process, the patterned epitaxial layer serves as a weakened structure, and can be automatically broken and a rough surface is thus formed. The weakened structure is formed with a specified height, and has pillar structures. The light-emitting structure is formed on the weakened structure. During a cooling process at room temperature, the weakened structure is automatically broken and a rough surface is thus formed. | 09-30-2010 |
| 20120074383 | DEVICE OF LIGHT-EMITTING DIODE - A LED device is provided. The LED device has a conductive carrier substrate, a light-emitting structure, a plurality of pillar structures, a dielectric layer, a first electrode and a second electrode. The light-emitting structure is located on the conductive carrier substrate. The pillar structures are located on the light-emitting structure. The dielectric layer is to cover a sidewall of the pillar structure. The first electrode is located over the pillar structure, and the second electrode is located on the conductive carrier substrate. | 03-29-2012 |
Donald Y. Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100038721 | METHOD OF FORMING A SINGLE METAL THAT PERFORMS N WORK FUNCTION AND P WORK FUNCTION IN A HIGH-K/METAL GATE PROCESS - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer over the capping layer, the metal layer having a first work function, treating a portion of the metal layer such that a work function of the portion of the metal layer changes from the first work function to a second work function, and forming a first metal gate from the untreated portion of the metal layer having the first work function and forming a second metal gate from the treated portion of the metal layer having the second work function. | 02-18-2010 |
| 20100044806 | INTEGRATED CIRCUIT METAL GATE STRUCTURE AND METHOD OF FABRICATION - A method of forming a gate structure is provided. The method includes providing a metal layer in the gate structure, the metal layer includes an oxygen-gettering composition. The metal layer getters oxygen from the interface layer, which may decrease the thickness of the interface layer. The gettered oxygen converts the metal layer to a metal oxide, which may act as a gate dielectric for the gate structure. A multi-layer metal gate structure is also provided including a oxygen-gettering metal layer, an oxygen-containing metal layer, and a polysilicon interface metal layer overlying a high-k gate dielectric. | 02-25-2010 |
| 20100048010 | SEMICONDUCTOR DEVICE GATE STRUCTURE INCLUDING A GETTERING LAYER - A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth. | 02-25-2010 |
| 20100048011 | METHOD OF PATTERNING A METAL GATE OF SEMICONDUCTOR DEVICE - Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process. | 02-25-2010 |
I Fen Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110158646 | MEDIUM ACCESS CONTROL DEVICE AND METHOD FOR OPTICAL PACKET-SWITCHED METRO WDM SLOTTED-RING NETWORKS - A medium access control (MAC) device and method for optical packet-switched metro wavelength division multiplexing (WDM) slotted-ring networks are used for providing quality of service (QoS) guarantees for isochronous traffic. The device includes a MAC processor and a distributed call admission control (CAC) module. The CAC module in each node of an optical packet-switched network is designed in a distributed manner, and flexibly allocates a reserved bandwidth to an isochronous traffic by a mean-rate-reservation method, controls a quota of the isochronous traffic below a quota ratio rH, resolves output contention by recording node locations forming a connection, and establishes a connection for each isochronous traffic. The MAC processor establishes a connection in the reserved bandwidth for each isochronous traffic between the nodes according to control information carried in a control channel, controls uploading, unloading, and erasing of a plurality of data channels, and updates corresponding contents in the control information. | 06-30-2011 |
Jui-I Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100093794 | Use of a Compound in Obtaining Cytoskeleton Blockage and Cell Elongation - A use of a compound in obtaining cytoskeleton and cell elongation is disclosed, the compound is 7-chloro-6-piperidin-1-yl-quinoline-5,8-dione with a chemical formula of C | 04-15-2010 |
Ling-Chiang Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080273364 | MEMORY STRUCTURE WITH EMBEDED MULTI-TYPE MEMORY - A memory includes a first-type memory; and a second-type memory, formed on the first-type memory, wherein the first-type memory is a nonvolatile memory with a stack of conductor/storage/conductor, and the second-type memory is a nonvolatile memory, a flash memory or another memory with a stack of conductor/storage/conductor. In addition, the nonvolatile memory can include a storage element for each memory cell, including a bottom electrode layer; a memory material layer, disposed over the bottom electrode layer, wherein the memory material has at least two physical states under different electric operation condition; and a top electrode layer, disposed over the memory material layer. | 11-06-2008 |
Mei-Ling Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100019318 | DEVICE FOR ESD PROTECTION CIRCUIT - A LDNMOS device for an ESD protection circuit including a P-type substrate and an N-type deep well region is provided. The P-type substrate includes a first area and a second area. The N-type deep well region is in the first and second areas of the P-type substrate. The LDNMOS device further includes a gate electrode disposed on the P-type substrate between the first and second areas, a P-type implanted region disposed in the first area of the P-type substrate, an N-type grade region disposed in the N-type deep well region of the first area, an N-type first doped region disposed in the N-type grade region, a P-type body region disposed in the N-type deep well region of the second area, an N-type second doped region disposed in the P-type body region, and a P-type doped region disposed in the P-type body region and adjacent to the N-type second doped region. | 01-28-2010 |
Paul C.p. Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120013486 | Optical Three-Dimensional Coordinate Sensor System and Method Thereof - The present invention relates an optical three-dimensional coordinate sensor system and method thereof. A plurality of light-emitting modules produce a plurality of light signals, and then a plurality of reflected light signals reflected by an object are received by a plurality of photodetectors. After receiving the reflected light signals, the photodetectors generate a plurality of photocurrents. A plurality of active pixel circuits receive the photocurrents and transform the photocurrents to a plurality of reflective optical voltages. A plurality of differential amplifier circuits (DAC) compare the reflective optical voltages and the background voltages, and then output a plurality of DAC output voltages of the reflected light signals. Afterward, a processing module detects the DAC output voltages and uses an algorithm to calculate the top three of the DAC output voltages to determine the three-dimensional coordinate of the object. | 01-19-2012 |
Ru-Pin Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090002581 | TUNABLE TERAHERTZ WAVELENGTH SELECTOR DEVICE USING MAGNETICALLY CONTROLLED BIREFRINGENCE OF LIQUID CRYSTALS - The present invention provides a tunable terahertz (THz) wavelength selector device, which includes a fixed phase retarder, a tunable phase retarder and a pair of linear polarizers to form a unit. The fixed phase retarder and tunable phase retarder basically utilizes liquid crystals to provide phase retardation, moreover, utilizing birefringence phenomenon possessed by liquid crystals can provide adequate phase retardation. The fixed phase retarder utilizes horizontal orientation of liquid crystal cell to provide fixed phase retardation, while the tunable phase retarder however utilizes homeotropic liquid crystal cell and a rotatable magnet to provide a tunable phase retardation, wherein the tunable phase retarder can provide the positive or negative phase retardation relative to the fixed phase retarder, based on the direction of the magnet's rotating axes and totally use the entire tunable range into adjusting frequencies which can pass through. Besides, the present invention can also serially connect multiple units described above so as to achieve a narrow enough band-pass bandwidth. | 01-01-2009 |
| 20090079929 | Method of alignments of liquid crystal employing magnetic thin films - Alignments of liquid crystal are obtained. A transparent magnetic thin film provides a homeotropic alignment of liquid crystal molecules. Or, a homeotropic or homogeneous alignment having an adjustable pretilt angle is further obtained through rubbing the transparent magnetic thin film. The present invention has a simple procedure with a low cost. The present invention is used in equipment with a plasma source while providing high transmittance, hardness and insulation. And the transparent magnetic thin film has potential uses in the applications of non-contact multi-domain alignment without extra procedure for alignment treatment. | 03-26-2009 |
| 20100053538 | STRUCTURE OF POLARIZING TERAHERTZ WAVE DEVICE - The Terahertz Polarizer structure of the present invention comprises of: A pair of parallel quartz layers for forming a rectangular cube with internal space, then a birefringent liquid crystal is placed in the internal space and sealed, and a pair of permanent magnets with reverse polarities are placed at both sides of the pair of fused silica layers. | 03-04-2010 |
| 20100110360 | Method of alignments of liquid crystal employing magnetic thin films - Alignments of liquid crystal are obtained. A transparent magnetic thin film provides a homeotropic alignment of liquid crystal molecules. Or, a homeotropic or homogeneous alignment having an adjustable pretilt angle is further obtained through rubbing the transparent magnetic thin film. The present invention has a simple procedure with a low cost. The present invention is used in equipment with a plasma source while providing high transmittance, hardness and insulation. And the transparent magnetic thin film has potential uses in the applications of non-contact multi-domain alignment without extra procedure for alignment treatment. | 05-06-2010 |
Shinh Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090317033 | INTEGRATED CIRCUIT AND PHOTONIC BOARD THEREOF - An integrated circuit (IC) including at least a first and a second logical blocks and a photonic board is provided. The photonic board connects with the first and the second logical blocks through a eutectic bonding technology, and communicates at least a logical signal of the first logical block to the second logical block by light conduction. | 12-24-2009 |
Ting-Sheng Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080303562 | DIVIDER - A divider is provided. The divider includes a first flip-flop, a flip-flop array, a first NOT gate, a second NOT gate, and a circuit. The first flip-flop can be triggered by a frequency signal. The first NOT gate is coupled between a positive output terminal of the last second flip-flop and the first flip-flop. The second NOT gate is coupled between the positive output terminal of the last second flip-flop and the circuit. The first NOT gate and the second NOT gate are controlled by the mode control signal for enabling. If N is an odd number, the circuit includes a wire, and if N is an even number, the circuit includes a third NOT gate. | 12-11-2008 |
Tzu Yi Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110194786 | DATA CONVERSION METHOD AND DATA CONVERSION DEVICE - A data conversion method and a data conversion device convert a large cubic three-dimensional image data to a plurality of pieces of small cubic one-dimensional image data, or convert a plurality of pieces of small cubic one-dimensional image data to a large cubic three-dimensional image data. The data conversion method includes the following steps, marking a three-dimensional index on three-dimensional image data; converting the three-dimensional index to a writing sequence index; inputting the three-dimensional image data to a buffer memory in sequence according to the writing sequence index; computing a reading sequence index according to the writing sequence index; outputting data blocks from the buffer memory in sequence according to the reading sequence index. Through the method and the device, use of the memory is reduced, and time for conversion is lowered. | 08-11-2011 |
| 20110279449 | METHOD FOR CALCULATING OCULAR DISTANCE - A method for calculating an ocular distance is presented. The method includes the following steps. A three-dimensional (3D) image display device generates one or more second display points and displays one or more virtual reference points. One or more calibration points are obtained, and these calibration points are generated through interaction by a user using an interaction component with the reference points. An ocular distance of the user is calculated according to a relative position between the display points, the calibration points, and the user. | 11-17-2011 |
Wei-Chung Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090097103 | Camera Lens and Related Image Reception Device Capable of Filtering Infrared Light and Reducing Production Cost - In order to prevent infrared from reducing image quality of an image reception device, the present invention discloses a camera lens capable of filtering infrared light. The camera lens includes a barrel, an aperture installed on the barrel for controlling the amount of input light, and an optical lens installed inside the barrel for filtering infrared and performing optical lens. | 04-16-2009 |
| 20090235219 | HIERARCHICAL ANALOG IC PLACEMENT SUBJECT TO SYMMETRY, MATCHING AND PROXIMITY CONSTRAINTS - A placement tool generates an optimal placement for a plurality of device modules within an analog integrated circuit (IC) subject to device matching, symmetry, and proximity constraints by first defining a multiple-level hierarchy of constraint groups, wherein each constraint group consists of elements that are subject to one of the placement constraints. Each element of each constraint group consists of either of one of the device modules or another one of the constraint groups residing at a lower level of the hierarchy. The tool then generates a hierarchical B*-tree representation of a trial placement for the IC including a separate node representing each constraint group of the hierarchy and a separate node for each of device module not included in any of the constraint groups. Each node representing a constraint group defines relative positions within the IC of each the device modules or lower level constraint groups forming the constraint group that are consistent with the placement constraint on the constraint group. The placement tool iteratively perturbs the hierarchical B*-tree to generate a sequence of trial placements for the IC design and then evaluates a cost function for each trial placement to select a best one of the trial placements as the optimal trial placement. | 09-17-2009 |
| 20120008201 | PROJECTION SCREEN AND MANUFACTURING METHOD THEREOF - A projection screen includes a base sheet, a surface roughness structure, a reflective layer, and a light absorption layer. The base sheet has a first side and a second side opposite to the first side. A plurality of first surfaces and second surfaces are formed on the first side, each first surface faces an optical projection system, and each second surface is disposed between two adjacent first surfaces and forms an angle with respect to a neighboring first surface. The surface roughness structure is formed on at least the first surfaces and capable of diffusing a light beam to a limited extent. The reflective layer is formed on the surface roughness structure and capable of reflecting most of the light beam diffused by the surface roughness structure to a limited extent towards a limited viewing cone, and the light absorption layer is formed on the second surfaces. | 01-12-2012 |
Yeh-Chin Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090237925 | White-light light-emitting diode (LED) road lamp composed of red, green and blue leds - The invention provides a white-light LED road lamp composed of red, green, and blue LED's. The road lamp includes a road lamp body, a heat-dissipating element, a constant-current source, and an LED board. The road lamp body is suspended at a specific height above the ground. Inside the road lamp body is disposed with the LED board connected with the heat-dissipating element. The side surface of the LED board opposite to the heat-dissipating element is electrically connected with a plurality of red, green, and blue LED's. The LED's are connected in series or parallel and driven by the constant-current source. | 09-24-2009 |
Yuan-Chun Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110117283 | SPRAY COATING SYSTEM - A spray coating system is provided. The spray coating system includes a spin support for supporting and spinning the substrate; a sprayer for applying a material to an upper surface of the substrate; a cup surrounding a lateral and lower region of the spin support, wherein an opening is located in an upper central region of the cup; an air supply mechanism for supplying air flows to a back surface of the substrate to prevent the material from adhering thereto, and an exhaust zone disposed below a slanted surface of the cup for exhausting the air flow and material. | 05-19-2011 |
Yu-Chiang Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120018719 | PHOTO TRANSISTOR - A phototransistor includes a substrate, a gate layer, a dielectric layer, an active layer, a source and a drain, and a light absorption layer. The gate layer is disposed on a top of the substrate, and the dielectric layer is disposed on a top of the gate layer. The active layer has a first bandgap and is disposed on a top of the dielectric layer, and the source and the drain are disposed on a top of the active layer. The light absorption layer has a second bandgap and is capped on the active layer, and the second bandgap is smaller than the first bandgap. | 01-26-2012 |
Yu-Lin Chao, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090294947 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip package structure includes a substrate, a chip, a thermal conductive layer, a plurality of signal contacts, and a molding compound. The substrate includes a plurality of first thermal conductive vias, a connecting circuit, and a plurality of signal vias electrically connected to the connecting circuit, and the substrate has a chip disposing region. The chip is disposed on the chip disposing region of the substrate and electrically connected to the signal vias through the connecting circuit. The thermal conductive layer is disposed over the substrate, connected to the first thermal conductive vias, and located above the chip disposing region. Besides, the thermal conductive layer has first openings exposing the signal vias. The signal contacts are respectively disposed in the first openings and connected to the signal vias. The molding compound encapsulates the chip. | 12-03-2009 |
| 20100267176 | LIGHT EMITTING APPARATUS AND FABRICATION METHOD THEREOF - A light emitting apparatus comprising a substrate, a first functional chip and a first light emitting component is provided. The substrate, the first functional chip, and the first light emitting component have a plurality of first bumps. In addition, the first functional chip has a plurality of first vias. The first light emitting component and the first functional chip are stacked on the substrate. Hence, the first light emitting component is electrically connected to the first functional chip and the substrate by the first vias and the first bumps. | 10-21-2010 |