Patent application number | Description | Published |
20090114935 | Light emitting diode and process for fabricating the same - A light emitting diode (LED) is provided. The LED at least includes a substrate, a saw-toothed multilayer, a first type semiconductor layer, an active emitting layer and a second type semiconductor layer. In the LED, the saw-tooth multilayer is formed opposite the active emitting layer below the first type semiconductor layer by an auto-cloning photonic crystal process. Due to the presence of the saw-tooth multilayer on the substrate of the LED, the scattered light form a back of the active emitting layer can be reused by reflecting and recycling through the saw-tooth multilayer. Thus, all light is focused to radiate forward so as to improve the light extraction efficiency of the LED. Moreover, the saw-tooth multilayer does not peel off or be cracked after any high temperature process because the saw-tooth multilayer has the performance of releasing thermal stress and reducing elastic deformation between it and the substrate. | 05-07-2009 |
20090274883 | NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD FOR FORMING THE SAME - An initial substrate structure for forming a nitride semiconductor substrate is provided. The initial substrate structure includes a substrate, a patterned epitaxial layer, and a mask layer. The patterned epitaxial layer is located on the substrate and is formed by a plurality of pillars. The mask layer is located over the substrate and covers a part of the patterned epitaxial layer. The mask layer includes a plurality of sticks and there is a space between the sticks. The space exposes a portion of an upper surface of the patterned epitaxial layer. | 11-05-2009 |
20100090312 | Nitride semiconductor structure and method for manufacturing the same - A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer. | 04-15-2010 |
20100243987 | DEVICE OF LIGHT-EMITTING DIODE AND METHOD FOR FABRICATING THE SAME - A device of a light-emitting diode and a method for fabricating the same are provided. The LED device is made by forming a patterned epitaxial layer, a light-emitting structure, etc., on a substrate. In a subsequent process, the patterned epitaxial layer serves as a weakened structure, and can be automatically broken and a rough surface is thus formed. The weakened structure is formed with a specified height, and has pillar structures. The light-emitting structure is formed on the weakened structure. During a cooling process at room temperature, the weakened structure is automatically broken and a rough surface is thus formed. | 09-30-2010 |
20120074383 | DEVICE OF LIGHT-EMITTING DIODE - A LED device is provided. The LED device has a conductive carrier substrate, a light-emitting structure, a plurality of pillar structures, a dielectric layer, a first electrode and a second electrode. The light-emitting structure is located on the conductive carrier substrate. The pillar structures are located on the light-emitting structure. The dielectric layer is to cover a sidewall of the pillar structure. The first electrode is located over the pillar structure, and the second electrode is located on the conductive carrier substrate. | 03-29-2012 |
20120119220 | NITRIDE SEMICONDUCTOR STRUCTURE - A nitride semiconductor substrate includes an epitaxy substrate, a patterned nitride semiconductor pillar layer, a nitride semiconductor layer, and a mask layer is provided. The nitride semiconductor pillar layer includes a plurality of first patterned arranged hollow structures and a plurality of second patterned arranged hollow structures formed among the first patterned arranged hollow structures. The second patterned arranged hollow structures have nano dimensions. The nitride semiconductor pillar layer is formed on the epitaxy substrate, and the nitride semiconductor layer is formed on the nitride semiconductor pillar layer. The mask layer covers surfaces of the nitride semiconductor pillar layer and the epitaxy substrate. | 05-17-2012 |
20120146190 | NITRIDE SEMICONDUCTOR TEMPLATE AND FABRICATING METHOD THEREOF - A nitride semiconductor template including a substrate, a mask layer, a first nitride semiconductor layer and a second nitride semiconductor is provided. The substrate has a plurality of trenches, each of the trenches has a bottom surface, a first inclined sidewall and a second inclined sidewall. The mask layer covers the second inclined sidewall and exposes the first inclined sidewall. The first nitride semiconductor layer is disposed over the substrate and the mask layer. The first nitride semiconductor layer fills the trenches and in contact with the first inclined sidewall. The first nitride semiconductor layer has voids located outside the trenches and parts of the mask layer are exposed by the voids. The first nitride semiconductor layer has a plurality of nano-rods. The second nitride semiconductor layer covers the nano-rods. The spaces between the nano-rods are not entirely filled by the second nitride semiconductor layer. | 06-14-2012 |
20120153338 | SUBSTRATE STRUCTURE AND FABRICATION THEREOF, AND LIGHT EMITTING DIODE DEVICES FABRICATED FROM THE SAME - A substrate structure is described, including a starting substrate, crystal piers on the starting substrate, and a mask layer. The mask layer covers an upper portion of the sidewall of each crystal pier, is connected between the crystal piers at its bottom, and is separated from the starting substrate by an empty space between the crystal piers. An epitaxial substrate structure is also described, which can be formed by growing an epitaxial layer over the above substrate structure form the crystal piers. The crystal piers may be broken after the epitaxial layer is grown. | 06-21-2012 |
20120161148 | NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes a base material, a patterned nitride semiconductor, a protection layer, and a nitride semiconductor layer. The patterned nitride semiconductor layer is located on the base material and includes a plurality of nanorod structures and a plurality of block patterns, and an upper surface of the nanorod structures is substantially coplanar with an upper surface of the block patterns. The protection layer covers a side wall of the nanorod structure sand a side wall of the block patterns. The nitride semiconductor layer is located on the patterned nitride semiconductor layer, and a plurality of nanopores are located between the nitride semiconductor layer and the patterned nitride semiconductor layer. | 06-28-2012 |
Patent application number | Description | Published |
20100038721 | METHOD OF FORMING A SINGLE METAL THAT PERFORMS N WORK FUNCTION AND P WORK FUNCTION IN A HIGH-K/METAL GATE PROCESS - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer over the capping layer, the metal layer having a first work function, treating a portion of the metal layer such that a work function of the portion of the metal layer changes from the first work function to a second work function, and forming a first metal gate from the untreated portion of the metal layer having the first work function and forming a second metal gate from the treated portion of the metal layer having the second work function. | 02-18-2010 |
20100044806 | INTEGRATED CIRCUIT METAL GATE STRUCTURE AND METHOD OF FABRICATION - A method of forming a gate structure is provided. The method includes providing a metal layer in the gate structure, the metal layer includes an oxygen-gettering composition. The metal layer getters oxygen from the interface layer, which may decrease the thickness of the interface layer. The gettered oxygen converts the metal layer to a metal oxide, which may act as a gate dielectric for the gate structure. A multi-layer metal gate structure is also provided including a oxygen-gettering metal layer, an oxygen-containing metal layer, and a polysilicon interface metal layer overlying a high-k gate dielectric. | 02-25-2010 |
20100048010 | SEMICONDUCTOR DEVICE GATE STRUCTURE INCLUDING A GETTERING LAYER - A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth. | 02-25-2010 |
20100048011 | METHOD OF PATTERNING A METAL GATE OF SEMICONDUCTOR DEVICE - Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process. | 02-25-2010 |
20130130488 | Method of Patterning a Metal Gate of Semiconductor Device - Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process. | 05-23-2013 |
20140091402 | INTEGRATED CIRCUIT METAL GATE STRUCTURE - A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer. | 04-03-2014 |
Patent application number | Description | Published |
20140328534 | DETECTION OF DEFECTS ON WAFER DURING SEMICONDUCTOR FABRICATION - Among other things, systems and techniques are provided for detecting defects on a wafer based upon non-correctable error data yielded from a scan of the wafer to determine a topology of the wafer. The non-correctable error data is reconstructed to generate a non-correctable error image map, which is transformed to generate a projection. In some embodiments, the non-correctable error image map is transformed via a feature extraction transform such as a Hough transform or a Radon transform. In some embodiments, the projection is compared to a set of rules to identify a signature in the non-correctable error image map indicative of a defect. | 11-06-2014 |
20140362359 | FLEXIBLE WAFER LEVELING DESIGN FOR VARIOUS ORIENTATION OF LINE/TRENCH - The present disclosure relates to a photolithography system having an ambulatory projection and/or detection gratings that provide for high quality height measurements without the use of an air gauge. In some embodiments, the photolithography system has a level sensor having a projection source that generates a measurement beam that is provided to a semiconductor substrate via a projection grating. A detector is positioned to receive a measurement beam reflected from the semiconductor substrate via a detection grating. An ambulatory element selectively varies an orientation of the projection grating and/or the detection grating to improve the measurement of the level sensor. By selectively varying an orientation of the projection and/or detection gratings, erroneous measurements of the level sensor can be eliminated. | 12-11-2014 |
20150015870 | Overlay Abnormality Gating by Z Data - The present disclosure relates to a method of monitoring wafer topography. A position and orientation of a plurality first alignment shapes disposed on a surface of a wafer are measured. Wafer topography as a function of wafer position is modeled by subjecting the wafer to an alignment which simultaneously minimizes misalignment between the wafer and a patterning apparatus and maximizes a focus of radiation on the surface. A non-correctable error is determined as a difference between the modeled wafer topography and a measured wafer topography. A maximum non-correctable error per field is determined for a wafer, and a mean variation in the maximum non-correctable error across each field within each wafer of a lot is determined, both within a layer and across layers. These values are then verified against a set of statistical process control rules to determine if they are within a specification limit of the manufacturing process. | 01-15-2015 |
Patent application number | Description | Published |
20100019318 | DEVICE FOR ESD PROTECTION CIRCUIT - A LDNMOS device for an ESD protection circuit including a P-type substrate and an N-type deep well region is provided. The P-type substrate includes a first area and a second area. The N-type deep well region is in the first and second areas of the P-type substrate. The LDNMOS device further includes a gate electrode disposed on the P-type substrate between the first and second areas, a P-type implanted region disposed in the first area of the P-type substrate, an N-type grade region disposed in the N-type deep well region of the first area, an N-type first doped region disposed in the N-type grade region, a P-type body region disposed in the N-type deep well region of the second area, an N-type second doped region disposed in the P-type body region, and a P-type doped region disposed in the P-type body region and adjacent to the N-type second doped region. | 01-28-2010 |
20130126972 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate of a first conductivity type, a fin, a gate, source and drain regions of a second conductivity type, and a first doped region of the second conductivity type. A plurality of isolation structures is formed on the substrate. The fin is disposed on the substrate between two adjacent isolation structures. The gate is disposed on the isolation structures and covers a portion of the fin, wherein the portion of the fin covered by the gate is of the first conductivity type. The source and drain regions is configured in the fin at respective sides of the gate. The first doped region is configured in the fin underlying the source and drain regions and adjoining the substrate. The first doped region has an impurity concentration lower than that of the source and drain regions. | 05-23-2013 |
20140027856 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge (ESD) includes a semiconductor substrate having the first conductive type, a well having the first conductive type, a buried layer having the second conductive type and a well having the second conductive type. The buried layer having a second conductive type is disposed in the semiconductor substrate under the well having the first conductive type. The well having the second conductive type disposed to divide the well having the first conductive type into a first well and a second well. The well having the second conductive type contacts the buried layer, and the well having the second conductive type and the buried layer are jointly used to isolate the first well from the second well. | 01-30-2014 |
20140057403 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided. A fin of a first conductivity type is formed on a substrate of the first conductivity type. A gate is formed on the substrate, wherein the gate covers a portion of the fin. Source and drain regions of a second conductivity type are formed in the fin at respective sides of the gate. A punch-through stopper (PTS) of the first conductivity type is formed in the fin underlying the gate and between the source and drain regions, wherein the PTS has an impurity concentration higher than that of the substrate. A first impurity of the second conductivity type is implanted into the PTS, so as to compensate the impurity concentration of the PTS. | 02-27-2014 |
Patent application number | Description | Published |
20090002581 | TUNABLE TERAHERTZ WAVELENGTH SELECTOR DEVICE USING MAGNETICALLY CONTROLLED BIREFRINGENCE OF LIQUID CRYSTALS - The present invention provides a tunable terahertz (THz) wavelength selector device, which includes a fixed phase retarder, a tunable phase retarder and a pair of linear polarizers to form a unit. The fixed phase retarder and tunable phase retarder basically utilizes liquid crystals to provide phase retardation, moreover, utilizing birefringence phenomenon possessed by liquid crystals can provide adequate phase retardation. The fixed phase retarder utilizes horizontal orientation of liquid crystal cell to provide fixed phase retardation, while the tunable phase retarder however utilizes homeotropic liquid crystal cell and a rotatable magnet to provide a tunable phase retardation, wherein the tunable phase retarder can provide the positive or negative phase retardation relative to the fixed phase retarder, based on the direction of the magnet's rotating axes and totally use the entire tunable range into adjusting frequencies which can pass through. Besides, the present invention can also serially connect multiple units described above so as to achieve a narrow enough band-pass bandwidth. | 01-01-2009 |
20090079929 | Method of alignments of liquid crystal employing magnetic thin films - Alignments of liquid crystal are obtained. A transparent magnetic thin film provides a homeotropic alignment of liquid crystal molecules. Or, a homeotropic or homogeneous alignment having an adjustable pretilt angle is further obtained through rubbing the transparent magnetic thin film. The present invention has a simple procedure with a low cost. The present invention is used in equipment with a plasma source while providing high transmittance, hardness and insulation. And the transparent magnetic thin film has potential uses in the applications of non-contact multi-domain alignment without extra procedure for alignment treatment. | 03-26-2009 |
20100053538 | STRUCTURE OF POLARIZING TERAHERTZ WAVE DEVICE - The Terahertz Polarizer structure of the present invention comprises of: A pair of parallel quartz layers for forming a rectangular cube with internal space, then a birefringent liquid crystal is placed in the internal space and sealed, and a pair of permanent magnets with reverse polarities are placed at both sides of the pair of fused silica layers. | 03-04-2010 |
20100110360 | Method of alignments of liquid crystal employing magnetic thin films - Alignments of liquid crystal are obtained. A transparent magnetic thin film provides a homeotropic alignment of liquid crystal molecules. Or, a homeotropic or homogeneous alignment having an adjustable pretilt angle is further obtained through rubbing the transparent magnetic thin film. The present invention has a simple procedure with a low cost. The present invention is used in equipment with a plasma source while providing high transmittance, hardness and insulation. And the transparent magnetic thin film has potential uses in the applications of non-contact multi-domain alignment without extra procedure for alignment treatment. | 05-06-2010 |
20120099063 | ALIGNMENT FILM FOR SPONTANEOUSLY ALIGNING LIQUID CRYSTAL - An alignment film for spontaneously aligning liquid crystal is used to align a plurality of liquid crystal grains and comprises a first substrate, a second substrate, a liquid crystal layer, a first transparent conductive layer, a second transparent conductive layer, a first alignment film and a second alignment film. The first and second alignment films are made of anodic aluminum oxide and have a plurality of nanometric pores respectively. The liquid crystal layer is interposed between the first and second alignment films. The nanometric pores of the first and second alignment films induce the liquid crystal grains to align spontaneously. Thereby, the problems of contamination, denatured material and non-uniform alignment, which are caused by the conventional liquid crystal alignment technology, can be solved. Further, the fabrication process of the alignment film can integrate with the current LCD process to fabricate a large-size LCD panel. | 04-26-2012 |
Patent application number | Description | Published |
20090097103 | Camera Lens and Related Image Reception Device Capable of Filtering Infrared Light and Reducing Production Cost - In order to prevent infrared from reducing image quality of an image reception device, the present invention discloses a camera lens capable of filtering infrared light. The camera lens includes a barrel, an aperture installed on the barrel for controlling the amount of input light, and an optical lens installed inside the barrel for filtering infrared and performing optical lens. | 04-16-2009 |
20090235219 | HIERARCHICAL ANALOG IC PLACEMENT SUBJECT TO SYMMETRY, MATCHING AND PROXIMITY CONSTRAINTS - A placement tool generates an optimal placement for a plurality of device modules within an analog integrated circuit (IC) subject to device matching, symmetry, and proximity constraints by first defining a multiple-level hierarchy of constraint groups, wherein each constraint group consists of elements that are subject to one of the placement constraints. Each element of each constraint group consists of either of one of the device modules or another one of the constraint groups residing at a lower level of the hierarchy. The tool then generates a hierarchical B*-tree representation of a trial placement for the IC including a separate node representing each constraint group of the hierarchy and a separate node for each of device module not included in any of the constraint groups. Each node representing a constraint group defines relative positions within the IC of each the device modules or lower level constraint groups forming the constraint group that are consistent with the placement constraint on the constraint group. The placement tool iteratively perturbs the hierarchical B*-tree to generate a sequence of trial placements for the IC design and then evaluates a cost function for each trial placement to select a best one of the trial placements as the optimal trial placement. | 09-17-2009 |
20120008201 | PROJECTION SCREEN AND MANUFACTURING METHOD THEREOF - A projection screen includes a base sheet, a surface roughness structure, a reflective layer, and a light absorption layer. The base sheet has a first side and a second side opposite to the first side. A plurality of first surfaces and second surfaces are formed on the first side, each first surface faces an optical projection system, and each second surface is disposed between two adjacent first surfaces and forms an angle with respect to a neighboring first surface. The surface roughness structure is formed on at least the first surfaces and capable of diffusing a light beam to a limited extent. The reflective layer is formed on the surface roughness structure and capable of reflecting most of the light beam diffused by the surface roughness structure to a limited extent towards a limited viewing cone, and the light absorption layer is formed on the second surfaces. | 01-12-2012 |
Patent application number | Description | Published |
20130075247 | METHOD AND SYSTEM FOR FORMING CHALCOGENIDE SEMICONDUCTOR MATERIALS USING SPUTTERING AND EVAPORATION FUNCTIONS - A method and system for forming a chalcogenide or chalcopyrite-based semiconductor material provide for the simultaneous deposition of metal precursor materials from a target and Se radials from a Se radical generation system. The Se radical generation system includes an evaporator that produces an Se vapor and a plasma chamber that uses a plasma to generate a flux of Se radicals. Multiple such deposition operations may take place in sequence, each having the deposition temperature accurately controlled. The deposited material may include a compositional concentration gradient or may be a composite material, and may be used as an absorber layer in a solar cell. | 03-28-2013 |
20130210190 | APPARATUS AND METHOD FOR PRODUCING SOLAR CELLS - A method and apparatus for forming a solar cell. The apparatus includes a housing defining a vacuum chamber and a rotatable substrate apparatus configured to hold a plurality of substrates on a plurality of surfaces wherein each of the plurality of surfaces are disposed facing an interior surface of the vacuum chamber. A first sputtering source is configured to deposit a plurality of absorber layer atoms of a first type over at least a portion of a surface of each one of the plurality of substrates. An evaporation source is disposed in a first subchamber of the vacuum chamber and configured to deposit a plurality of absorber layer atoms of a second type over at least a portion of the surface of each one of the plurality of substrates. A first isolation source is configured to isolate the evaporation source from the first sputtering source. | 08-15-2013 |
20140131193 | APPARATUS AND METHOD FOR FORMING THIN FILMS IN SOLAR CELLS - Apparatus for forming a solar cell comprises a housing defining a chamber including a substrate support. A sputtering source is configured to deposit particles of a first type over at least a portion of a surface of a substrate on the substrate support. An evaporation source is configured to deposit a plurality of particles of a second type over the portion of the surface of the substrate. A cooling unit is provided between the sputtering source and the evaporation source. A control system is provided for controlling the evaporation source based on a rate of mass flux emitted by the evaporation source. | 05-15-2014 |
20140131198 | SOLAR CELL FORMATION APPARATUS AND METHOD - Apparatuses for forming material films on a solar cell substrate of substantially uniform thickness and processes for forming the same are disclosed. The process performed in the apparatuses is physical vapor deposition (PVD) in some embodiments. In one embodiment, an apparatus includes a specially configured flow aperture. In another embodiment, an apparatus includes moveable shutters which open and close in synchronization with a rotating drum on which substrates are mounted for processing. In other embodiments, the apparatus includes a variable power supply or drum speed control which automatically vary the power supply to the apparatus or drum speed respectively in synchronization with the rotating drum. | 05-15-2014 |
20140193939 | METHOD AND SYSTEM FOR FORMING ABSORBER LAYER ON METAL COATED GLASS FOR PHOTOVOLTAIC DEVICES - An apparatus for forming a solar cell includes a housing defining a vacuum chamber, a rotatable substrate support, at least one inner heater and at least one outer heater. The substrate support is inside the vacuum chamber configured to hold a substrate. The at least one inner heater is between a center of the vacuum chamber and the substrate support, and is configured to heat a back surface of a substrate on the substrate support. The at least one outer heater is between an outer surface of the vacuum chamber and the substrate support, and is configured to heat a front surface of a substrate on the substrate support. | 07-10-2014 |
20140302634 | APPARATUS AND METHOD FOR PRODUCING SOLAR CELLS - A method and apparatus for forming a solar cell. The apparatus includes a housing defining a vacuum chamber and a rotatable substrate apparatus configured to hold a plurality of substrates on a plurality of surfaces. A first sputtering source is configured to deposit a plurality of absorber layer atoms of a first type over at least a portion of a surface of each one of the plurality of substrates. An evaporation source is configured to deposit a plurality of absorber layer atoms of a second type over at least a portion of the surface of each one of the plurality of substrates. | 10-09-2014 |
Patent application number | Description | Published |
20090294947 | CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A chip package structure includes a substrate, a chip, a thermal conductive layer, a plurality of signal contacts, and a molding compound. The substrate includes a plurality of first thermal conductive vias, a connecting circuit, and a plurality of signal vias electrically connected to the connecting circuit, and the substrate has a chip disposing region. The chip is disposed on the chip disposing region of the substrate and electrically connected to the signal vias through the connecting circuit. The thermal conductive layer is disposed over the substrate, connected to the first thermal conductive vias, and located above the chip disposing region. Besides, the thermal conductive layer has first openings exposing the signal vias. The signal contacts are respectively disposed in the first openings and connected to the signal vias. The molding compound encapsulates the chip. | 12-03-2009 |
20100267176 | LIGHT EMITTING APPARATUS AND FABRICATION METHOD THEREOF - A light emitting apparatus comprising a substrate, a first functional chip and a first light emitting component is provided. The substrate, the first functional chip, and the first light emitting component have a plurality of first bumps. In addition, the first functional chip has a plurality of first vias. The first light emitting component and the first functional chip are stacked on the substrate. Hence, the first light emitting component is electrically connected to the first functional chip and the substrate by the first vias and the first bumps. | 10-21-2010 |
20120249176 | TEST STRUCTURE AND MEASUREMENT METHOD THEREOF - A test structure including a substrate, at least one conductive plug, a first conductive trace and a second conductive trace is provided. The substrate has a first area and a second area. The at lest one conductive plug is disposed in the substrate in the first area, wherein the conductive plug does not penetrate through the substrate. | 10-04-2012 |
20140138075 | HEAT EXCHANGER AND SEMICONDUCTOR MODULE - A heat exchanger suitable for cooling a heat source is provided, wherein a bypass channel formed in the heat exchanger has a width greater than a width of other channels to reduce a flow resistance of a fluid and a pumping power for driving a system. That is, under the same pumping power loss, more fluid is driven to achieve a better heat dissipation effect. By applying the heat exchanger, electronic devices are bonded to a top of the heat exchanger through a supporting substrate. In this way, heat generated when the electronic devices are is transferred to the heat exchanger through the supporting substrate and dissipated to the outside via the heat exchanger. Since the distance of heat transfer is decreased, the thermal resistance generated by an interface between the devices is reduced to improve heat transfer efficiency and heat dissipation effect. | 05-22-2014 |