Patent application number | Description | Published |
20140101234 | MULTI-CLOUD COMMUNICATION SYSTEM - A multi-cloud communication system includes a plurality of clouds, each of which has a cloud server and a plurality of servers connected with the cloud server. The cloud server has a service information of the servers. When a first cloud server of a first cloud transmits a request information to a second cloud server of a second cloud, the second cloud server determines a level relationship between the first and second clouds, and acquires a target data from at least a second server of the second cloud according to the request information and the service information. The target data is encoded according to the level relationship, and then transmitted to at least a first server of the first cloud through the second cloud server and the first cloud server. The first server, according to the level relationship, decodes the encoded target data to obtain the target data. | 04-10-2014 |
20140165142 | INTERACTIVE CLOUD COMMUNICATION SYSTEM - An interactive cloud communication system includes at least a client end and a cloud. The client end includes a browser. The cloud includes a cloud server module and a server module connected to the cloud server module. The cloud server module includes a websocket authentication unit. When the client end connects to the cloud through the browser, the cloud server module performs an authentication mechanism to the client end by the websocket authentication unit for opening at least a transmission channel allowing information transmission between the client end and the cloud. | 06-12-2014 |
20140351319 | PORTABLE ELECTRONIC APPARATUS AND PORTABLE CLOUD COMPUTING SYSTEM - A portable electronic apparatus includes an operating system comprising an application layer, an application framework layer, a libraries layer and a kernel layer. The application layer includes a cloud user interface allowing a user to perform an interactive function. The application framework layer includes a plurality of cloud components and at least a cloud service. The libraries layer includes a plurality of cloud managers. The kernel layer includes a cloud server driver, which is connected to the cloud managers to start the cloud service, so that the cloud service calls one of the cloud components according to the interactive function. By such configuration, the portable electronic apparatus of this invention can carry a private cloud to provide the service of a portable personal cloud. | 11-27-2014 |
Patent application number | Description | Published |
20090092812 | Transparent PVC sheet for cutting-off infrared and ultra-violet - A heat-insulating transparent PVC sheet is made by a non-coating process for cutting-off infrared and ultra-violet, which production method of the heat-insulating transparent PVC sheet uses the conventional process for making PVC sheets, and a mixture of specific formula of PVC resin, plasticizer, inorganic heat-insulating particles or other additive is used directly to make the heat-insulating transparent PVC sheet to keep the properties of PVC and to provide transparency, low haze and an excellent effect for cutting-off infrared and ultra-violet. | 04-09-2009 |
20100068494 | Heat-insulating transparent PVC sheet - A heat-insulating transparent PVC sheet useful to replace the glass or affixed to the glass is made by a non-coating process for cutting-off infrared and ultra-violet, which production method is an improved traditional process for producing the PVC sheets, and in the production a specific formula of PVC blends containing PVC resin, plasticizer, inorganic heat-insulating particles and other additives is directly used to produce the PVC sheet to keep the properties of PVC and to provide transparency, low haze and an excellent effect for cutting-off infrared and ultra-violet. | 03-18-2010 |
20130267645 | WEATHER-RESISTANT CROSSLINKED POLYOLEFIN COMPOSITION, POLYOLEFIN SHEET MADE FROM THE SAME AND METHOD FOR MAKING THE SHEET - A weather-resistant crosslinked polyolefin composition is a novel formula containing a comprehensive mixture constituted by crosslinking agent, antistatic agent, TiO | 10-10-2013 |
20150104698 | ALUMINUM FILM PACKAGING MATERIALS USED FOR LITHIUM BATTERIES - A method for lithium aluminum film packaging materials, with water, high temperature and corrosion resistance, the substrate layer, and then layer, aluminum foil layer, anti-corrosion layer, adhesive layer and the inner layer together constitute from the outermost to innermost layer laminate structure in which one side of the aluminum foil layer, or both side surface of the conductive coating material to said coating and curing anticorrosive layer, and the use of fluorine-containing polyurethane resin constituting the laminated rubber layer and the inner layer of corrosion between the adhesive layer, used lithium batteries as plastic film packaging applications, it can promote lithium battery with Merit water resistance, high temperature resistance and corrosion resistance, and enhance the use of lithium batteries in years. | 04-16-2015 |
Patent application number | Description | Published |
20140252618 | METHOD FOR FORMING INTERCONNECT STRUCTURE THAT AVOIDS VIA RECESS - A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. The dielectric material layer is patterned to form a plurality of vias therein. A first metal layer is formed on the dielectric material layer, wherein the first metal layer fills the plurality of vias. The first metal layer is planarized so that the top thereof is co-planar with the top of the dielectric material layer to form a plurality of first metal features. A stop layer is formed on top of each of the plurality of first metal features, wherein the stop layer stops a subsequent etch from etching into the plurality of the first metal features. | 09-11-2014 |
20140252622 | Method for Forming Recess-Free Interconnect Structure - A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. An oxygen-rich layer is formed over the dielectric material layer. The dielectric material layer and the oxygen-rich layer are patterned to form a plurality of vias in the semiconductor substrate. A barrier layer is formed in the plurality of vias and on the dielectric material layer leaving a portion of the oxygen-rich layer exposed. A metal layer is formed on the barrier layer and on the exposed portion of the oxygen-rich layer, wherein the metal layer fills the plurality of vias. The semiconductor substrate is annealed at a predetermined temperature range and at a predetermined pressure to transform the exposed portion of the oxygen-rich layer into a metal-oxide stop layer. | 09-11-2014 |
20140273434 | METHOD OF FABRICATING COPPER DAMASCENE - A method of fabricating a semiconductor device includes forming a non-conductive layer over a semiconductor substrate. A low-k dielectric layer is formed over the non-conductive layer. The low-k dielectric layer is etched and stopped at the non-conductive layer to form an opening. A plasma treatment is performed on the substrate to convert the non-conductive layer within the opening into a conductive layer. The opening is filled with a copper-containing material in an electroless copper bottom up fill process to form a copper-containing plug. The copper-containing plug is planarized so that the top of the copper-containing plug is co-planar with the top of the low-k dielectric layer. The substrate is heated to form a self-forming barrier layer on the sidewalls of the copper-containing plug. | 09-18-2014 |
20150118850 | Lithography using Multilayer Spacer for Reduced Spacer Footing - A method embodiment for patterning a semiconductor device includes forming a plurality of mandrels over a substrate, and forming a multilayer spacer layer over the plurality of mandrels. The multilayer spacer layer is formed by conformably depositing a spacer layer over the plurality of mandrels and treating the spacer layer with plasma. The plurality of mandrels is exposed by etching a top portion of the multilayer spacer layer, thereby forming a multilayer spacer. | 04-30-2015 |
20150132947 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include: forming an opening in a dielectric layer, the opening exposing a non-conductive layer disposed over a semiconductor substrate; forming a self-assembled monolayer (SAM) within the opening and over the non-conductive layer; forming a catalytic layer within the opening and over the SAM; filling the opening having the SAM and the catalytic layer with a conductive material to form a plug; and forming a barrier layer on sidewalls of the plug. | 05-14-2015 |
20150145134 | Method for Forming Recess-Free Interconnect Structure - A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. An oxygen-rich layer is formed over the dielectric material layer. The dielectric material layer and the oxygen-rich layer are patterned to form a plurality of vias in the semiconductor substrate. A barrier layer is formed in the plurality of vias and on the dielectric material layer leaving a portion of the oxygen-rich layer exposed. A metal layer is formed on the bather layer and on the exposed portion of the oxygen-rich layer, wherein the metal layer fills the plurality of vias. The semiconductor substrate is annealed at a predetermined temperature range and at a predetermined pressure to transform the exposed portion of the oxygen-rich layer into a metal-oxide stop layer. | 05-28-2015 |
20150214102 | Interconnect Structures Comprising Flexible Buffer Layers - A structure includes a substrate, a low-k dielectric layer over the substrate, and a conductive barrier layer extending into the low-k dielectric layer. The conductive barrier layer includes a sidewall portion. A metal line in the low-k dielectric layer adjoins the conductive barrier layer. An organic buffer layer is between the sidewall portion of the conductive barrier layer and the low-k dielectric layer. | 07-30-2015 |
20150270170 | Method of Semiconductor Integrated Circuit Fabrication - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features. | 09-24-2015 |
20150270215 | VIA PRE-FILL ON BACK-END-OF-THE-LINE INTERCONNECT LAYER - The present disclosure relates to a metal interconnect layer formed using a pre-fill process to reduce voids, and an associated method. In some embodiments, the metal interconnect layer has a dielectric layer disposed over a substrate. An opening with an upper portion above a horizontal plane and a lower portion below the horizontal plane extends downwardly through the dielectric layer. A first conductive layer fills the lower portion of the opening. An upper barrier layer is disposed over the first conductive layer covering bottom and sidewall surfaces of the upper portion of the opening. A second conductive layer is disposed over the upper barrier layer filling the upper portion of the opening. | 09-24-2015 |
Patent application number | Description | Published |
20090011612 | METHOD OF SHORTENING PHOTORESIST COATING PROCESS - A method of shortening a photoresist coating process for a plurality of wafers is provided, wherein the photoresist coating process includes a first coating operation to a first wafer using a first photoresist liquid and a second coating operation to a second wafer using a second photoresist liquid. The method includes performing a dummy dispense operation of the second photoresist liquid within the period of the backend part of the first coating operation that needs no nozzle. | 01-08-2009 |
20130038336 | Probe Calibration Device and Calibration Method - A calibration device applied for a test apparatus with at least a first probe and a second probe, the calibration device comprising: a first testing region and a second testing region, the first testing region and the second testing region divides into n×n sensing units respectively, the first testing region for generating n×n average electricity corresponding to a contact degree of the first probe contacted with the calibration device, and the second testing region for generating another n×n average electricity corresponding to a contact degree of the second probe contacted with the calibration device, and the pitch is the distance between the center of the first testing region to the center of the second testing region that is the same as that of the center of the first probe to the center of the second probe. | 02-14-2013 |
20150103585 | High stability static random access memory cell - A Static Random Access Memory (SRAM) cell is a latch circuit formed with two inverters each formed with a PMOS transistor and an NMOS transistor. The latch circuit is coupled to a capacitor through a switch. When the switch is switched on, the stability of data stored in the SRAM cell will be enhanced. When the switch is switched off, data can be written to the SRAM cell quickly. | 04-16-2015 |