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| 20080254640 | METHOD OF REMOVING MATERIAL LAYER AND REMNANT METAL - A method of removing material layer is disclosed. First, a semiconductor substrate is fixed on a rotating platform, where a remnant material layer is included on the surface of the semiconductor substrate. Afterward, an etching process is carried out. In the etching process, the rotating platform is rotated, and an etching solution is sprayed from a center region and a side region of the rotating platform toward the semiconductor substrate until the material layer is removed. Since the semiconductor substrate is etched by the etching solution sprayed from both the center region and the side region of the rotating platform, the etching uniformity of the semiconductor substrate is improved. | 10-16-2008 |
| 20090102058 | METHOD FOR FORMING A PLUG STRUCTURE AND RELATED PLUG STRUCTURE THEREOF - A method for forming a plug structure by utilizing a punching through process and the related plug structure are provided. An opening is defined in a substrate, and an unwanted oxide residue is disposed on a bottom of the opening. A glue layer is subsequently formed over the substrate. Portions of the glue layer are disposed on the sidewall and bottom of the opening, and cover the oxide. Thereafter, the portion of the first glue layer disposed at the bottom of the opening is punched through until the substrate is exposed so as to remove the oxide. Next, the opening is filled with a conductive structure. | 04-23-2009 |
| 20100015771 | METHOD OF FABRICATING STRAINED SILICON TRANSISTOR - A method of fabricating a strained silicon transistor is provided. Amorphous silicon is formed below the transistor region before the transistor is formed. By using the tensile/compressive strainer, amorphous silicon is recrystallized to form a strained silicon layer. In addition, the dopants in the well can be driven in and activated by using the same annealing process with the amorphous silicon recrystallization. | 01-21-2010 |
| 20110104895 | METHOD FOR FORMING A PLUG STRUCTURE - A method for forming a plug structure includes the following steps. A substrate is provided. The substrate includes a MOS device with a source/drain region, a dielectric layer disposed on the MOS device, an opening defined in the dielectric layer, and a first glue layer disposed on a sidewall and a bottom of the opening. A portion of the first glue layer disposed at the bottom of the opening is punched through to expose the source/drain region. A barrier layer is formed over the substrate after the first glue layer is punched through. The opening is filled with a conductive structure, wherein the barrier layer disposed at the bottom of the opening is remained when the conductive structure is filled into the opening. | 05-05-2011 |
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| 20110020994 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method of forming a semiconductor device is described. First, a substrate is provided. Thereafter, a gate structure including, from bottom to top, a high-k layer, a work function metal layer, a wetting layer, a polysilicon layer and a mask layer is formed on the substrate. Afterwards, a spacer is formed on the sidewall of the gate structure. Source/drain regions are then formed in the substrate beside the gate structure. Further, an interlayer dielectric layer is formed over the substrate. Thereafter, a portion of the interlayer dielectric layer is removed to expose the surface of the mask layer. Afterwards, the mask layer and the polysilicon layer are sequentially removed to expose the surface of the wetting layer. A selective chemical vapor deposition process is then performed, so as to bottom-up deposit a metal layer from the surface of the wetting layer. | 01-27-2011 |
| 20110140206 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate, a gate structure, a spacer and source/drain regions is provided. The gate structure is on the substrate, wherein the gate structure includes, from bottom to top, a high-k layer, a work function metal layer, a wetting layer and a metal layer. The spacer is on a sidewall of the gate structure. The source/drain regions are in the substrate beside the gate structure. | 06-16-2011 |
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| 20080224232 | SILICIDATION PROCESS FOR MOS TRANSISTOR AND TRANSISTOR STRUCTURE - A silicidation process for a MOS transistor and a resulting transistor structure are described. The MOS transistor includes a silicon substrate, a gate dielectric layer, a silicon gate, a cap layer on the silicon gate, a spacer on the sidewalls of the silicon gate and the cap layer, and S/D regions in the substrate beside the silicon gate. The process includes forming a metal silicide layer on the S/D regions, utilizing plasma of a reactive gas to react a surface layer of the metal silicide layer into a passivation layer, removing the cap layer and then reacting the silicon gate into a fully silicided gate. | 09-18-2008 |
| 20090068854 | SILICON NITRIDE GAP-FILLING LAYER AND METHOD OF FABRICATING THE SAME - A method for fabricating a silicon nitride gap-filling layer is provided. A pre-multi-step formation process is performed to form a stacked layer constituting as a dense film on a substrate. Then, a post-single step deposition process is conducted to form a cap layer constituting as a sparse film on the stacked layer, wherein the cap layer has a thickness of at least 10% of the total film thickness. | 03-12-2009 |
| 20090090395 | METHOD OF REMOVING PARTICLES FROM WAFER - A method of removing particles from a wafer is provided. The method is adopted after a process for removing unreactive metal of a salicide process or after a salicide process and having oxide residue remaining on a wafer or after a chemical vapor deposition (CVD) process that resulted with particles on a wafer. The method includes performing at least two cycles (stages) of intermediate rinse process. Each cycle of the intermediate rinse process includes conducting a procedure of rotating the wafer at a high speed first, and then conducting a procedure of rotating the wafer at a low speed. | 04-09-2009 |
