Patent application number | Description | Published |
20110058093 | AUTO FOCUSING METHOD USING VCM ACTUATOR - The present disclosure relates to an auto focusing method using a VCM (voice coil motor) actuator, the method of using the VCM actuator to upwardly move a lens position, to obtain a most-focused upward position value, and downwardly move the lens position to automatically adjust the lens focus, the method comprising: obtaining an auto focus (AF) upward position value, which is an upward position value of a lens when the lens is most focused by upwardly moving the lens to capture an image; determining whether a difference between the AF upward position value and an AF downward position value of a code value which is a bit value corresponding to the AF upward position value is smaller than a pre-set level; and implementing the auto focusing the code value if the difference is smaller than the pre-set level, and using a hysteresis table of the VCM actuator to select a code value corresponding to a downward position value most approximate to the AF upward position value in a downward position value column and to implement the auto focusing adjustment using the corrected code value, if the difference is not smaller than the pre-set level. | 03-10-2011 |
20130070148 | CAMERA MODULE - The present invention relates to a camera module having an auto focus function, the module including a lens unit having at least one lens, a barrel into which the lens unit is inserted, and connected by a VCM (Voice Coil Motor) actuator, and an image sensor discretely positioned from the lens unit to convert light having passed the lens unit to an electrical signal, where the VCM actuator includes a gap of a reference distance position value which is a position of an object catering to a lens focal length according to the camera module, and information on a focus-met lens position value, and adjusts an initial position of the lens by using the gap of reference distance position value of the lens position value during operation of the camera module. | 03-21-2013 |
20130146031 | VAPOR GAS DISCHARGING APPARATUS FOR HYBRID ELECTRIC VEHICLE - A vapor gas discharging apparatus for a hybrid electric vehicle (HEV), which includes a vapor line disposed between a canister and a fuel tank, wherein a purge line may be connected to the canister for transferring vapor gas from the canister to an engine, may include a discharging nipple formed to the canister and employed to supply air to the canister, an air supply line connected to the discharging nipple of the canister for supplying the air to the discharging nipple, a two-way valve connected to an end of an exhaust pipe and an end of the air supply line, and controlled for selectively communicating air flow between the air supply line and the exhaust pipe or between the air supply line and the outside of the air supply line, and a conduction member disposed in the air supply line between the two-way valve and the discharging nipple. | 06-13-2013 |
20150185587 | CAMERA MODULE - The present invention relates to a camera module having an auto focus function, the module including a lens unit having at least one lens, a barrel into which the lens unit is inserted, and connected by a VCM (Voice Coil Motor) actuator, and an image sensor discretely positioned from the lens unit to convert light having passed the lens unit to an electrical signal, where the VCM actuator includes a gap of a reference distance position value which is a position of an object catering to a lens focal length according to the camera module, and information on a focus-met lens position value, and adjusts an initial position of the lens by using the gap of reference distance position value of the lens position value during operation of the camera module. | 07-02-2015 |
Patent application number | Description | Published |
20100072559 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a string gate structure and a method of manufacturing the same suppress leakage current. The semiconductor device includes a selection gate and a memory gate. The channel region of the selection gate has a higher impurity concentration than that of the memory gate. Impurities may be implanted at different angles to form the channel regions having different impurity concentrations. | 03-25-2010 |
20100214844 | Memory system and programming method thereof - Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming the selected memory cell depending on the adjusted program-verify-voltage. | 08-26-2010 |
20110199829 | Nonvolatile Memory Device, Programming Method Thereof And Memory System Including The Same - Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages. | 08-18-2011 |
20120003800 | Methods of Forming Nonvolatile Memory Devices Having Vertically Integrated Nonvolatile Memory Cell Sub-Strings Therein and Nonvolatile Memory Devices Formed Thereby - Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series. | 01-05-2012 |
20120068247 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Provided are three-dimensional semiconductor devices. The devices may include gap-fill insulating patterns configured to upwardly extend from a substrate and an electrode structure defined by sidewalls of the gap-fill insulating patterns. Vertical structures may be provided between adjacent ones of the gap-fill insulating patterns to penetrate the electrode structure, and the vertical structures may include first and second rows of the vertical structures. A separation pattern may be provided between the first and second rows of vertical structures and include a separation semiconductor layer. The separation pattern extends along a direction parallel to the first and second rows of vertical structures. | 03-22-2012 |
20120068255 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess is provided, which extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells are provided on the substrate. This vertical stack of nonvolatile memory cells includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers are provided, which extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength. | 03-22-2012 |
20120081958 | NONVOLATILE MEMORY DEVICES AND METHODS FORMING THE SAME - Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other. | 04-05-2012 |
20120081959 | MEMORY SYSTEM AND PROGRAMMING METHOD THEREOF - Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming the selected memory cell depending on the adjusted program-verify-voltage. | 04-05-2012 |
20120104484 | NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile memory device includes a substrate, a stacked structure with conductive materials and first insulating materials and the conductive materials and the first insulating materials are alternately stacked on the substrate, and a plurality of pillars in contact with the substrate and the pillars extend through the stacked structure in a direction perpendicular to the substrate. The device also includes information storage layers between the conductive materials and the first insulating materials, and second insulating materials between the first insulating materials and the pillars. | 05-03-2012 |
20120112264 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure. | 05-10-2012 |
20120120732 | NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF - A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed. | 05-17-2012 |
20120199897 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed. | 08-09-2012 |
20120286344 | NON-VOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - A non-volatile may include a plurality of device isolation patterns disposed in a substrate to define an active region extending in a first direction, a gate pattern disposed on the substrate to extend in a second direction crossing the first direction, a charge storing pattern disposed between the active region and the gate pattern, a blocking dielectric layer disposed between the charge storing pattern and the gate pattern, and a tunnel dielectric layer disposed between the active region and the charge storing pattern. A center area of a top surface of the active region includes one of a rounded surface or a tip, and the center area of the top surface of the active region corresponds to an uppermost portion of the active region and the uppermost portion of the active region is disposed at a level lower than a lowermost portion of the gate pattern. | 11-15-2012 |
20120327715 | NONVOLATILE MEMORY DEVICES HAVING VERTICALLY INTEGRATED NONVOLATILE MEMORY CELL SUB-STRINGS THEREIN - Methods of forming nonvolatile memory devices according to embodiments of the invention include techniques to form highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series. | 12-27-2012 |
20130114345 | NONVOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF - According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the serially-connected selection transistors. A control logic is configured to perform a program operation for setting a threshold voltage of at least one of the serially-connected selection transistors. | 05-09-2013 |
20130140623 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device may include gap-fill insulating layers extending upward from a substrate, an electrode structure delimited by sidewalls of the gap-fill insulating layers, vertical structures provided between adjacent ones of the gap-fill insulating layers to penetrate the electrode structure, and at least one separation pattern extending along the gap-fill insulating layers and penetrating at least a portion of the electrode structure. The separation pattern may include at least one separation semiconductor layer. | 06-06-2013 |
20130329496 | NONVOLATILE MEMORY DEVICE AND ERASE METHOD THEREOF - A method of erasing a nonvolatile memory device, which includes a plurality of memory blocks each formed of a plurality of strings, includes applying an erase voltage to a well of a selected memory block of the memory blocks, each memory block including at least two dummy cells located between a string or ground selection transistor and memory cells; and applying or inducing different levels of voltages to respective gates of the at least two dummy cells. | 12-12-2013 |
20140016408 | NONVOLATILE MEMORY DEVICES HAVING VERTICALLY INTEGRATED NONVOLATILE MEMORY CELL SUB-STRINGS THEREIN - Nonvolatile memory devices according to embodiments of the invention include highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series. | 01-16-2014 |
20140029344 | NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - Provided is a programming method of a nonvolatile memory device. The nonvolatile memory device includes a substrate and a plurality of memory cells which are stacked in the direction perpendicular to the substrate. The programming method applies a first voltage to a selected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be programmed, applies a second voltage to an unselected bit line connected to at least two memory strings in same column including a memory cell of the plurality of memory cell to be program-prohibited, applies a third voltage to a selected string selection line connected to at least two memory strings in same row, applies a fourth voltage to an unselected string selection line connected to at least two memory strings in same row, and applies a program operation voltage to a plurality of word lines, each word line connected to each corresponding memory cell in the memory string, wherein the first to third voltages are positive voltages. | 01-30-2014 |
20140042520 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength. | 02-13-2014 |
20140104945 | NONVOLATILE MEMORY DEVICES AND METHODS FORMING THE SAME - Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other. | 04-17-2014 |
20140162423 | SEMICONDUCTOR DEVICE COMPRISING STRING STRUCTURES FORMED ON ACTIVE REGION - A semiconductor device having a string gate structure and a method of manufacturing the same suppress leakage current. The semiconductor device includes a selection gate and a memory gate. The channel region of the selection gate has a higher impurity concentration than that of the memory gate. Impurities may be implanted at different angles to form the channel regions having different impurity concentrations. | 06-12-2014 |
20140198572 | STRING SELECTION STRUCTURE OF THREE-DIMENSIONAL SEMICONDUCTOR DEVICE - A three-dimensional semiconductor device includes first and second selection lines stacked one on the other. An upper line horizontally crosses over the first and second selection lines. First and second vertical patterns vertically cross the first and second selection lines. The first and second vertical patterns are connected in common to the upper line. Each of the first and second vertical patterns constitutes first and second selection transistors that are connected in series to each other. The first selection transistors of the first and second vertical patterns are controlled by the first and second selection lines, respectively. | 07-17-2014 |
20140254271 | Nonvolatile Memory Device and Read Method Thereof - A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed. | 09-11-2014 |
20150037951 | Three-Dimensional Semiconductor Devices and Methods of Fabricating the Same - Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed. | 02-05-2015 |
20150061545 | METHOD AND APPARATUS FOR CONTROLLING LIGHTING - A lighting control method and an electronic device using the same are provided. The method includes receiving pattern information for controlling lighting, generating lighting control information including brightness level information corresponding to operation time information based on the received pattern information, and transmitting the lighting control information. | 03-05-2015 |
20150187791 | METHODS OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure. | 07-02-2015 |
20150214243 | NONVOLATILE MEMORY DEVICES AND METHODS FORMING THE SAME - Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other. | 07-30-2015 |
20150340093 | NONVOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF - According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the serially-connected selection transistors. A control logic is configured to perform a program operation for setting a threshold voltage of at least one of the serially-connected selection transistors. | 11-26-2015 |
20150348983 | SEMICONDUCTOR DEVICE INCLUDING A STACK HAVING A SIDEWALL WITH RECESSED AND PROTRUDING PORTIONS - A semiconductor device includes a substrate, a stack, and channel structures penetrating the stack. The stack includes gate electrodes and insulating layers alternately and repeatedly stacked on the substrate, and extending in a first direction. The channel structures in a first row are spaced apart from each other in the first direction. The stack includes a first sidewall that includes first recessed portions and first protruding portions. Each of first recessed portions is defined by an adjacent pair of the first recessed portions. Each of the first recessed portions has a shape recessed toward a first region of the stack between an adjacent pair of the channel structures of the first row. Each of the first recessed portions has a width that decreases in a direction toward the first region when measured along the first direction. | 12-03-2015 |
20150357345 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength. | 12-10-2015 |