| Patent application number | Description | Published |
|---|
| 20080242075 | METHOD FOR FORMING NON-VOLATILE MEMORY DEVICES - According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability. | 10-02-2008 |
| 20080283879 | TRANSISTOR HAVING GATE DIELECTRIC LAYER OF PARTIAL THICKNESS DIFFERENCE AND METHOD OF FABRICATING THE SAME - A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates. | 11-20-2008 |
| 20080296638 | Semiconductor device and method of manufacturing the same - A semiconductor device includes an active pattern on a substrate, the active pattern including a protrusion with a lower surface on the substrate and an upper surface opposite the lower surface, a width of the protrusion gradually decreasing from the lower surface to the upper surface, the upper surface of the protrusion being sharp and defining a first active region of the active pattern along a first direction, isolation layer patterns on the substrate in recesses at both sides of the active pattern, the isolation layer patterns exposing the first active region, a gate structure on the first active region and on the isolation layer patterns, the gate structure extending along a second direction, the first and second directions being perpendicular to each other, and source/drain regions under the first active region at both sides of the gate structure. | 12-04-2008 |
| 20090065850 | NON-VOLATILE MEMORY DEVICES - According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability. | 03-12-2009 |
| 20090203178 | Memory device and method of manufacturing the same - A example embodiment may provide a memory device that may include an active pattern on a semiconductor substrate, a first charge trapping layer pattern on the active pattern, a first gate electrode on the first charge trapping layer pattern, a second charge trapping layer pattern on a sidewall of the active pattern in a first direction, a second gate electrode on the second charge trapping layer pattern in the first direction, and/or a source/drain region in the active pattern. The memory device may have improved integration by forming a plurality of charge trapping layer patterns on the same active pattern. | 08-13-2009 |
| 20100035398 | Field effect transistor and method for manufacturing the same - A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate. | 02-11-2010 |
| 20100038702 | Nonvolatile memory device and methods of forming the same - Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The memory cells may each include a memory layer having a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer and a side gate formed on the memory layer. According to example embodiments, larger scale integration of the nonvolatile memory devices may be achieved and the reliability of the memory devices may increase. | 02-18-2010 |
| 20100330761 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Exposed are a semiconductor device and method of fabricating the same. The device includes an insulation film that is disposed between an active pattern and a substrate, which provides various improvements. This structure enhances the efficiency of high integration and offers an advanced structure for semiconductor devices. | 12-30-2010 |
| 20110042746 | SINGLE TRANSISTOR MEMORY DEVICE HAVING SOURCE AND DRAIN INSULATING REGIONS AND METHOD OF FABRICATING THE SAME - A single transistor floating-body dynamic random access memory (DRAM) device includes a floating body located on a semiconductor substrate and a gate electrode located on the floating body, the floating body including an excess carrier storage region. The DRAM device further includes source and drain regions respectively located at both sides of the gate electrode, and leakage shielding patterns located between the floating body and the source and drain regions. Each of the source and drain regions contact the floating body, which may be positioned between the source and drain regions. The floating body may also laterally extend under the leakage shielding patterns, which may be arranged at outer sides of the gate electrode. | 02-24-2011 |
