| Patent application number | Description | Published |
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| 20090173986 | Semiconductor Devices Including Gate Structures and Leakage Barrier Oxides - Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed. | 07-09-2009 |
| 20090256177 | Semiconductor device including an ohmic layer - In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance. | 10-15-2009 |
| 20090298273 | METHODS OF FORMING RECESSED GATE ELECTRODES HAVING COVERED LAYER INTERFACES - Methods of forming a gate electrode can be provided by forming a trench in a substrate, conformally forming a polysilicon layer to provide a polysilicon conformal layer in the trench defining a recess surrounded by the polysilicon conformal layer, wherein the polysilicon conformal layer is formed to extend upwardly from a surface of the substrate to have a protrusion and the protrusion has a vertical outer sidewall adjacent the surface of the substrate, forming a tungsten layer in the recess to form an upper surface that includes an interface between the polysilicon conformal layer and the tungsten layer, and forming a capping layer being in direct contact with top surfaces of the polysilicon conformal layer and the tungsten layer without any intervening layers. | 12-03-2009 |
| 20090325371 | Methods of Forming Integrated Circuit Devices Having Stacked Gate Electrodes - A method of forming a gate electrode of a semiconductor device is provided, the method including: forming a plurality of stacked structures each comprising a tunnel dielectric layer, a first silicon layer for floating gates, an intergate dielectric layer, a second silicon layer for control gates, and a mask pattern, on a semiconductor substrate in the stated order; forming a first interlayer dielectric layer between the plurality of stacked structures so that a top surface of the mask pattern is exposed; selectively removing the mask pattern of which the top surface is exposed; forming a third silicon layer in an area from which the hard disk layer was removed, and forming a silicon layer comprising the third silicon layer and the second silicon layer; recessing the first interlayer dielectric layer so that an upper portion of the silicon layer protrudes over the he first interlayer dielectric layer; and forming a metal silicide layer on the upper portion of the silicon layer. | 12-31-2009 |
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| 20080312088 | Field effect transistor, logic circuit including the same and methods of manufacturing the same - Provided are a field effect transistor, a logic circuit including the same and methods of manufacturing the same. The field effect transistor may include an ambipolar layer that includes a source region, a drain region, and a channel region between the source region and the drain region, wherein the source region, the drain region, and the channel region may be formed in a monolithic structure, a gate electrode on the channel region, and an insulating layer separating the gate electrode from the ambipolar layer, wherein the source region and the drain region have a width greater than that of the channel region in a second direction that crosses a first direction in which the source region and the drain region are connected to each other. | 12-18-2008 |
| 20090020399 | Electromechanical switch and method of manufacturing the same - Provided is an electromechanical switch and a method of manufacturing the same. The electromechanical switch includes an elastic conductive layer that moves by the application of an electric field, wherein the elastic conductive layer includes at least one layer of graphene. | 01-22-2009 |
| 20090032795 | Schottky diode and memory device including the same - A Schottky diode and a memory device including the same are provided. The Schottky diode includes a first metal layer and an Nb-oxide layer formed on the first metal layer. | 02-05-2009 |
| 20090073859 | Magnetic tracks, information storage devices using magnetic domain wall movement, and methods of manufacturing the same - Information storage devices and methods of manufacturing the same are provided. A magnetic track of the information storage device includes a magnetic layer in which at least one magnetic domain forming region and at least one magnetic domain wall forming region are alternately disposed in a lengthwise direction. The at least one magnetic domain forming regions has a different magnetic anisotropic energy relative to the at least one magnetic domain wall forming region. An intermediate layer is formed under the magnetic layer. The intermediate layer includes at least one first material region and at least one second material region. Each of the at least one first material regions and the at least one second material regions corresponds to one of the at least one magnetic domain forming regions and the at least one magnetic domain wall forming regions. | 03-19-2009 |
| 20090130492 | Information storage devices using magnetic domain wall movement and methods of manufacturing the same - Information storage devices and methods of manufacturing the same are provided. An information storage device includes a magnetic layer formed on an underlayer. The underlayer has at least one first region and at least one second region. The first and second regions have different crystallinity characteristics. The magnetic layer has at least one third region formed on the at least one first region and at least one fourth region formed on the at least one second region. The third and fourth regions have different magnetic anisotropic energy constants. | 05-21-2009 |
| 20090250752 | Methods of fabricating semiconductor device having a metal gate pattern - A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H | 10-08-2009 |
