Patent application number | Description | Published |
20080266976 | NAND MEMORY DEVICE AND PROGRAMMING METHODS - A NAND Flash memory device is described that can reduce circuitry noise during program operations. The memory includes bit lines that can be electrically coupled together to charge share their respective voltage potentials prior to performing a discharge operation on the bit lines. | 10-30-2008 |
20090073772 | PROGRAM METHOD WITH OPTIMIZED VOLTAGE LEVEL FOR FLASH MEMORY - A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the percentage of the data bits that failed programming verification during the previous programming cycle and were not correctly programmed into the memory array. This allows for a faster on average program operation and a more accurate match of the subsequent increase in the programming voltage to the non-volatile memory device, the specific region or row being programmed and any changes due to device wear. In one embodiment of the present invention the manufacturing process/design and/or specific memory device is characterized by generating a failed bit percentage to programming voltage increase profile to set the desired programming voltage delta/increase. In another embodiment of the present invention, methods and apparatus are related for the programming of data into non-volatile memory devices and, in particular, NAND and NOR architecture Flash memory. | 03-19-2009 |
20090097331 | INTERLEAVED INPUT SIGNAL PATH FOR MULTIPLEXED INPUT - System and method for latching input signals from multiplexed signal lines. An input signal path includes a command path and an address path. In one embodiment, a command latch of the command path latches commands from the input signals and the address path includes a plurality of address latches that latch addresses from the input signals in an interleaved manner. In another embodiment, the command path includes a plurality of command latches that latch commands from the input signals in an interleaved manner and the address path includes a plurality of address latches that latch addresses from the input signals in an interleaved manner. | 04-16-2009 |
20090116283 | Controlling a memory device responsive to degradation - Embodiments of the present invention disclosed herein include devices, systems and methods, such as those directed to non-volatile memory devices and systems capable of determining a degradation parameter associated with one or more memory cells. Disclosed devices and systems according to embodiments of the present invention include those that utilize the degradation parameter to adjust control signals coupled to the memory cells. | 05-07-2009 |
20100074020 | CHARGE PUMP OPERATION IN A NON-VOLATILE MEMORY DEVICE - A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump during a verify operation. The first load voltage is subsequently recharged by charge sharing from the second load voltage so that the charge pump is not initially necessary for recharging the first load voltage. | 03-25-2010 |
20100124115 | PROGRAM AND SENSE OPERATIONS IN A NON-VOLATILE MEMORY DEVICE - Methods for programming and sensing in a memory device, a data cache, and a memory device are disclosed. In one such method, all of the bit lines of a memory block are programmed or sensed during the same program or sense operation by alternately multiplexing the odd or even page bit lines to the dynamic data cache. The dynamic data cache is comprised of dual SDC, PDC, DDC | 05-20-2010 |
20100142283 | PROGRAM METHOD WITH OPTIMIZED VOLTAGE LEVEL FOR FLASH MEMORY - A non-volatile memory device and programming process is described that increases the programming voltage of successive programming cycles in relation to the percentage of the data bits that failed programming verification during the previous programming cycle and were not correctly programmed into the memory array. This allows for a faster on average program operation and a more accurate match of the subsequent increase in the programming voltage to the non-volatile memory device, the specific region or row being programmed and any changes due to device wear. In one embodiment of the present invention the manufacturing process/design and/or specific memory device is characterized by generating a failed bit percentage to programming voltage increase profile to set the desired programming voltage delta/increase. In another embodiment of the present invention, methods and apparatus are related for the programming of data into non-volatile memory devices and, in particular, NAND and NOR architecture Flash memory. | 06-10-2010 |
20110122699 | CONTROLLING A MEMORY DEVICE RESPONSIVE TO DEGRADATION - Embodiments of the present invention disclosed herein include devices, systems and methods, such as those directed to non-volatile memory devices and systems capable of determining a degradation parameter associated with one or more memory cells. Disclosed devices and systems according to embodiments of the present invention include those that utilize the degradation parameter to adjust control signals coupled to the memory cells. | 05-26-2011 |
20110179218 | METHOD FOR READING A MULTILEVEL CELL IN A NON-VOLATILE MEMORY DEVICE - A non-volatile memory device has a memory array comprising a plurality of memory cells. The array can operate in either a multilevel cell or single level cell mode and each cell has a lower page and an upper page of data. The memory device has a data latch for storing flag data and a cache latch coupled to the data latch. A read method comprises initiating a lower page read of a memory cell and reading, from the data latch, flag data that indicates whether a lower page read operation is necessary. | 07-21-2011 |
20110280078 | CHARGE PUMP OPERATION IN A NON-VOLATILE MEMORY DEVICE - A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump during a verify operation. The first load voltage is subsequently recharged by charge sharing from the second load voltage so that the charge pump is not initially necessary for recharging the first load voltage. | 11-17-2011 |
20110292732 | NAND MEMORY DEVICE AND PROGRAMMING METHODS - A NAND Flash memory device reduces circuitry noise during program operations. The memory includes bit lines that are electrically coupled together to charge share their respective voltage potentials prior to performing a discharge operation on the bit lines. A NAND flash cell is programmed by coupling a first memory array bit line to a program voltage to program the memory cell, biasing a second memory array bit line to a ground potential, wherein the second memory array bit line is located adjacent to the first memory array bit line, activating at least one first transistor to electrically coupling the first and second memory array bit lines together, and activating at least one second transistor to electrically couple the first and second memory array bit lines to a discharge potential. | 12-01-2011 |
20110296093 | PROGRAM AND SENSE OPERATIONS IN A NON-VOLATILE MEMORY DEVICE - Methods for programming and sensing in a memory device, a data cache, and a memory device are disclosed. In one such method, all of the bit lines of a memory block are programmed or sensed during the same program or sense operation by alternately multiplexing the odd or even page bit lines to the dynamic data cache. The dynamic data cache comprises dual SDC, PDC, DDC1, and DDC2 circuits such that one set of circuits is coupled to the odd page bit lines and the other set of circuits is coupled to the even page bit lines. | 12-01-2011 |
20120224428 | CHARGE PUMP OPERATION IN A NON-VOLATILE MEMORY DEVICE - A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump during a verify operation. The first load voltage is subsequently recharged by charge sharing from the second load voltage so that the charge pump is not initially necessary for recharging the first load voltage. | 09-06-2012 |
20120287722 | DYNAMIC DATA CACHES, DECODERS AND DECODING METHODS - Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding method may be used in flash memory devices. A single column select line may be provided to select a plurality of cached bytes, while a second select line selects a byte of the selected plurality. The column select line may be routed parallel to bit lines carrying data, while the second select line may be routed perpendicular to the bit lines. | 11-15-2012 |
20130117604 | APPARATUSES AND METHODS FOR OPERATING A MEMORY DEVICE - Subject matter described pertains to apparatuses and methods for operating a memory device. | 05-09-2013 |
20140008806 | STAIR STEP FORMATION USING AT LEAST TWO MASKS - Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed. | 01-09-2014 |
20140078836 | USING A REFERENCE BIT LINE IN A MEMORY - Methods, memories and systems may include charging a sense node to a logic high voltage level, and supplying charge to a bit line and to a reference bit line for a precharge period that is based, at least in part, on a time for a voltage of the reference bit line to reach a reference voltage. A memory cell that is coupled to the bit line may be selected after the precharge period, and a clamp voltage may be set based, at least in part, on the voltage of the reference bit line. If a voltage level of the bit line is less than the clamp voltage level during a sense period, charge may be drained from the sense node, and a state of the memory cell may be determined based, at least in part, on a voltage level of the sense node near an end of the sense period. | 03-20-2014 |
20140138840 | STAIR STEP FORMATION USING AT LEAST TWO MASKS - Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed. | 05-22-2014 |
20140149786 | APPARATUSES AND METHODS FOR OPERATING A MEMORY DEVICE - Subject matter described pertains to apparatuses and methods for operating a memory device. | 05-29-2014 |
20140195734 | POWER MANAGEMENT - Methods, and apparatus configured to perform such methods, providing peak power management are useful in mitigating excessive current levels within a multi-die package. For example, a method might include generating a clock signal in a particular die of a plurality of dies, counting pulses of the clock signal in a wrap-around counter in each die of the plurality of dies, and pausing an access operation for the particular die of the plurality of dies at a designated point until a value of the wrap-around counter matches an assigned counter value of the particular die. | 07-10-2014 |
20140233318 | DYNAMIC DATA CACHES, DECODERS AND DECODING METHODS - Examples described include dynamic data caches (DDCs), decoders and decoding methods that may fit into a smaller width area. The DDCs, decoders and decoding method may be used in flash memory devices. A single column select line may be provided to select a plurality of cached bytes, while a second select line selects a byte of the selected plurality. The column select line may be routed parallel to bit lines carrying data, while the second select line may be routed perpendicular to the bit lines. | 08-21-2014 |
20140241060 | SUB-BLOCK DECODING IN 3D MEMORY - Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. Sub-blocks may comprise a vertical string of memory cells including a source select transistor and a drain select transistor. An apparatus may include two or more drain select lines, of which a first drain select line is coupled to a drain select transistor in a first sub-block of a first block and to a drain select transistor in a first sub-block of a second block. A second drain select line in the apparatus may be coupled to a drain select transistor in a second sub-block of the first block and to a drain select transistor in a second sub-block of the second block. Other apparatuses and methods are described. | 08-28-2014 |
20140241092 | SUB-BLOCK DISABLING IN 3D MEMORY - Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. One such sub-block may comprise a vertical string of memory cells including a select transistor. An apparatus may include a sub-block disabling circuit. The sub-block disabling circuit may include a content-addressable memory. The content-addressable memory may receive an address, including a block address and a sub-block address. The content addressable memory may output a signal to disable a tagged sub-block if the received address includes the block address and the sub-block address associated with the tagged sub-block. The sub-block disabling circuit may further include a plurality of drivers to drive one or more of the select transistors based on the signal. Other apparatus and methods are described. | 08-28-2014 |