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Chang Sik
Chang Sik Cho, Daejeon KR
| Patent application number | Description | Published |
|---|---|---|
| 20080310502 | INTER MODE DETERMINATION METHOD FOR VIDEO ENCODER - The present invention relates to a method for a video encoder to determine an inter mode. The video encoder selects initial candidate modes by using inter mode information of a previous frame so as to determine the inter mode, estimates a macroblock having the greatest correlation with a current macroblock in the previous frame, compares the rate-distortion cost of the corresponding macroblock and the rate-distortion cost of the selected mode from among the initial candidate modes, and determines whether to terminate the inter mode determination process early. When the early termination condition is satisfied, the video encoder determines the candidate mode having the minimum rate-distortion cost from among the initial candidate modes as the inter mode of the current macroblock, and terminates the inter mode determination process early. When the early termination condition is not satisfied, the video encoder additionally performs an inter prediction process by selecting additional candidate modes, and determines the candidate mode having the determined minimum rate-distortion cost as the inter mode of the current macroblock. | 12-18-2008 |
| 20090016443 | INTER MODE DETERMINATION METHOD FOR VIDEO ENCODING - The present invention relates to a method for a video encoder to determine an inter mode. The video encoder selects first search modes by using optimized inter mode information of a correlation macroblock having the same position as a current macroblock in a previous frame, in order to determine the inter mode. The video encoder compares a rate-distortion cost of the correlation macroblock and a rate-distortion cost of the mode that is selected as the minimum cost mode from among the first search modes, and determines whether to terminate an inter mode determination process early. When the early termination condition is satisfied, the video encoder determines the search mode having the minimum rate-distortion cost from among the first search modes as the optimized inter mode of the current macroblock, and terminates the inter mode determination process early. When the early termination condition is not satisfied, the video encoder selects second search modes to additionally perform an inter prediction process, and determines the corresponding search mode having the minimum rate-distortion cost as the optimized inter mode of the current macroblock. | 01-15-2009 |
| 20090022123 | Apparatus and method for providing contents sharing service on network - The present invention relates to a network-based contents sharing service providing device and method. A contents provider stores at least one content in a memory and manages it, classifies information on shared contents to be shared with the contents receiver according to a predetermined reference, generates a shared contents list by making information on the classified shared contents into a list, manages the list, and provides the shared contents list to the corresponding contents receiver when there is a contents receiver for sharing shared contents from among the contents receivers in the service area in which the contents provider is positioned. A contents receiver presents the shared contents list to the contents receiving user, receives at least one shared content from the contents provider through downloading or streaming according to selection of the contents receiving user having acquired the list, and performs it. Accordingly, the contents receiving user can freely use various contents of the contents provider positioned in the service area such as his portable terminal. | 01-22-2009 |
| 20090046779 | Method and apparatus for determining block mode using bit-generation probability estimation in moving picture coding - Provided are a method and apparatus for determining a block mode using bit-generation probability estimation in motion picture coding. In H.264 video coding for Internet protocol (IP)-television (TV), the method and apparatus first determine whether or not a current block mode is a skip mode or a direct-prediction mode using bit-generation probability estimation, thereby reducing the amount of computation. By minimizing the amount of computation for determining a block mode, it is possible to increase an encoding rate and also minimize deterioration in image quality. | 02-19-2009 |
| 20110130205 | GAME GRAMMAR-BASED PACKET CAPTURE AND ANALYSIS APPARATUS AND METHOD FOR CONDUCTING GAME TEST - A game grammar-based packet capture and analysis apparatus for conducting game test, includes: a packet capture unit for capturing packets of game data transmitted and received between a game client and a game server; a packet analysis unit for analyzing the packets captured by the packet capture unit to generate a game grammar based on analyzed results. Further, the game grammar-based packet capture and analysis apparatus includes a load generation unit for generating packets in compliance with the game grammar to apply the packets to the game server as a load. | 06-02-2011 |
Chang Sik Hong, Daegu KR
| Patent application number | Description | Published |
|---|---|---|
| 20120082957 | DENTAL MODEL ARTICULATOR - Disclosed is a dental model articulator configured to combine maxillary and mandibular dental model casts with each other. The dental model articulator includes a frame, an arm member rotatably and reciprocatively supported to the frame, an elastic bias unit frontward elastically pressing the arm member with respect to the frame, a first connecting unit formed in the arm member to be connected with the maxillary dental model cast, and a second connecting unit connected to the frame to move reciprocatvely through at least one penetration hole and combined with the mandibular dental model cast. | 04-05-2012 |
Chang Sik Kim, Hongseong-Gun KR
| Patent application number | Description | Published |
|---|---|---|
| 20100024218 | METHOD OF MAKING BEARING USING ULTRASONIC NANO CRYSTAL SURFACE MODIFICATION TECHNOLOGY - A method of making a bearing includes providing a bearing intermediate, which is unfinished while having an overall shape of a finished bearing product; and repeatedly impacting a surface of the bearing intermediate at one or more ultrasonic frequencies to modify characteristics of the bearing intermediate. The resulting bearing intermediate or finished bearing product includes nano-size grains at or underneath the surface. | 02-04-2010 |
Chang Sik Lee, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110021942 | APPARATUS AND METHOD OF ANALYZING CONSTITUENTS OF GAS IN ORAL CAVITY AND ALVEOLAR GAS - An apparatus and a method of analyzing constituents of gas in an oral cavity and exhaled breath is disclosed. The apparatus for analyzing the constituents of gas in the oral cavity and exhaled breath according to the present invention includes a filter to filter the outside gas by adsorbing polar molecules and non-polar molecules in the outside air and by removing water in the outside air in order to use the outside gas as carrier gas. The apparatus can also include a plurality of solenoid valves for controlling the flow of a carrier gas; a sensor for detecting components of the exhaled breath; a pump to draw the gas in the oral cavity or the exhaled breath and the carrier gas and discharge the gases to the outside; a control unit for controlling the components of the apparatus; and a display device to display results calculated by the control unit. | 01-27-2011 |
Chang Sik Lee, Cheonan-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120028963 | NOVEL HYDROXAMATE DERIVATIVE, A PRODUCTION METHOD FOR THE SAME, AND A PHARMACEUTICAL COMPOSITION COMPRISING THE SAME - The present invention relates to hydroxamate derivatives, isomers thereof, pharmaceutically acceptable salts thereof, hydrates thereof, or solvates thereof, the use thereof for preparing pharmaceutical compositions, pharmaceutical compositions containing the same, a method of treating disease using the compositions, and a method for preparing the hydroxamate derivatives. | 02-02-2012 |
Chang Sik Lim, Jincheon-Gun KR
| Patent application number | Description | Published |
|---|---|---|
| 20110197863 | EXHAUST GAS RECIRCULATION VALVE IN VEHICLE - An exhaust gas recirculation valve in a vehicle has two valves that are controlled individually by using one driving source. The exhaust gas recirculation valve enables secure operation of a vehicle even if the driving source is out of order. The exhaust gas recirculation EGR valve includes a driving unit having a driving motor for rotating a motor shaft and an interlocking unit for receiving rotational force from the motor shaft. A rod portion moves upon reception of the rotational force. A valve unit at an end portion of the rod portion controls a flow rate of the exhaust gas. A valve housing is coupled to the driving unit as one unit and has an EGR port and a bypass port. The interlocking unit includes a valve return member for rotating the motor shaft forcibly to make the valve unit to move to an initial position. | 08-18-2011 |
Chang Sik Lim, Chungbuk KR
| Patent application number | Description | Published |
|---|---|---|
| 20100319798 | VACUUM PUMP FOR VEHICLES - Disclosed is a vacuum pump for vehicles which reduces noise of exhaust air generated during operation of the vacuum pump. | 12-23-2010 |
Chang Sik Yoo, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080304334 | SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE HAVING ON-DIE TERMINATION CIRCUIT AND ON-DIE TERMINATION METHOD - A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation. | 12-11-2008 |
| 20090059680 | Integrated Circuit Memory Devices That Support Selective Mode Register Set Commands - A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation. An enable signal may be provided from the memory controller to a second one of the integrated circuit memory devices over a signal line between the memory controller and the second integrated circuit memory device to thereby enable implementation of the mode register set command for the second integrated circuit memory device during the mode register set operation. Moreover, the disable signal may not be provided to the second integrated circuit memory device during the mode register set operation, and the enable signal may not be provided to the first integrated circuit memory device during the mode register set operation. Related systems, devices and additional methods are also discussed. | 03-05-2009 |
| 20100054053 | Integrated Circuit Memory Devices Including Mode Registers Set Using A Data Input/Output Bus - An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data input/output pins may be further configured to provide data to the memory controller from the memory cell array during a data read operation. A mode register may be configured to store information defining an operational characteristic of the memory device, and the mode register may be configured to be set using the data input/output bus. Related methods, systems, and additional devices are also discussed. | 03-04-2010 |
| 20100329040 | DATA ALIGNMENT CIRCUIT AND METHOD OF SEMICONDUCTOR MEMORY APPARATUS - A data alignment circuit of a semiconductor memory apparatus includes: a data strobe clock phase control block configured to control a phase of a data strobe clock signal in response to a strobe delay code and generate a delayed strobe clock signal; a plurality of data phase control blocks configured to control phases of input data in response to data delay codes and generate delayed data; a plurality of data alignment blocks configured to latch the delayed data in response to the delayed strobe clock signal and generate latched data and aligned data; and a delay code generation block configured to perform an operation of determining phases of the latched data and generate the strobe delay code and the data delay codes. | 12-30-2010 |
| 20110141841 | SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE HAVING ON-DIE TERMINATION CIRCUIT AND ON-DIE TERMINATION METHOD - A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation synchronized to an external clock. The synchronous semiconductor memory device having a data output circuit for performing a data output operation synchronously to the external clock includes the ODT circuit for generating ODT up and down signals having the same timing as data output up and down signals for the data output operation, to perform the ODT operation. | 06-16-2011 |
Chang Sik Yoon, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100122284 | BROADCASTING RECEIVER AND METHOD OF PROCESSING EMERGENCY ALERT MESSAGE - A broadcasting receiver capable of receiving cable broadcasting and a method of processing an emergency alert message thereof are disclosed. Each time an emergency alert message is received, each time an execution of a received emergency alert message such as a channel switching and/or a message display is needed, or each time an executed emergency alert message is terminated, a host within a broadcasting receiver according to the present invention provides each state information to a data broadcasting associated application within the broadcasting receiver. Accordingly, when a host executes an emergency alert message, it is able to prevent abnormal operations of a data broadcasting associated application. | 05-13-2010 |
Chang Sik Yun, Seoul KR
Chang-Sik Choi, Cheonkanam-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080196799 | Steel Sheet for Deep Drawing Having Excellent Secondary Work Embrittlement Resistance, Fatigue Properties and Plating Properties, and Method for Manufacturing the Same - A steel sheet for deep drawing used for automobiles, and a method for manufacturing the same are disclosed. The steel sheet comprises, by weight %, C: 0.010% or less, Si: 0.02% or less, Mn: 0.06˜1.5%, P: 0.15% or less, S: 0.020% or less, Sol. Al: 0.10˜0.40%, N: 0.010% or less, Ti: 0.003˜0.010%, Nb: 0.003˜0.040%, B: 0.0002˜0.0020%, and the balance of Fe and other unavoidable impurities, wherein the composition of Ti, Al, B, and N satisfies the relationship: 1.0<(Ti[%]+Al[%]/16+6B[%])/3.43N[%]<4.1, and wherein the composition of Nb, Al, and C satisfies the relationship; 0.7<(Nb[%]+Al[%]/20)/7.75C[%]<3.5. The steel sheet exhibits excellent secondary work embrittlement, fatigue properties of welded joints, and an appealing plated surface as well as excellent formability. | 08-21-2008 |
Chang-Sik Kim, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100013506 | PROBE PAD, SUBSTRATE HAVING A SEMICONDUCTOR DEVICE, METHOD OF TESTING A SEMICONDUCTOR DEVICE AND TESTER FOR TESTING A SEMICONDUCTOR DEVICE - In an embodiment, a semiconductor device is tested using a probe pad that includes a probing region with which a probe needle makes contact, and a sensing region bordering an edge of the probing region. Electrical signals are applied, and measured results indicate the probe needle's location relative to a test position on the semiconductor device. | 01-21-2010 |
Chang-Sik Kim, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090073780 | Memory device for detecting bit line leakage current and method thereof - A memory device may include a plurality of bit line pairs, at least one local data line pair, and/or a bit line leakage current measurement unit. The at least one local data line pair may be connected to the bit line pairs in response to a column selection signal. The bit line leakage current measurement unit may be configured to monitor a direct drain quiescent current (IDDQ) flowing though at least one measurement line connected to the at least one local data line pair in response to a test mode signal. | 03-19-2009 |
Chang-Sik Lim, Cheongju-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110227502 | CIRCUIT AND METHOD FOR GENERATING PWM SIGNAL FOR DC-DC CONVERTER USING DIMMING SIGNAL AND LED DRIVING CIRCUIT FOR BACKLIGHT HAVING THE SAME - A pulse width modulation (PWM) signal generating circuit that generates a PWM signal for a DC-DC converter using a dimming signal is provided. The PWM signal generating circuit includes a normal PWM signal generator configured to generate a normal PWM signal based on a clock signal provided to the DC-DC converter, and a compensation PWM signal generator configured to generate a compensation PWM signal based on the clock signal and the dimming signal. | 09-22-2011 |
Chang-Sik Yoo, Goori City KR
| Patent application number | Description | Published |
|---|---|---|
| 20110169591 | FILTER CUT-OFF FREQUENCY CORRECTION CIRCUIT - A filter cut-off frequency correction circuit, inputted with a step function increasing from a first voltage to a second voltage, comprises a linear passive filter, for integrating the step function to obtain a third voltage; a first comparator, outputting a first high-level signal when the third voltage is greater than a first predetermined reference voltage; a second comparator, outputting a second high-level signal in a first period from the time that the second voltage is applied to the time that the first comparator outputs the first high-level signal; a counter, for counting a number of clock pulses of a reference clock inputted in the first period; a digital block, for calculating a variation rate of time constant according to the number of clock pulses of the reference clock, and generating a correction code; and a filter, for correcting the cut-off frequency according to the correction code. The correction circuit can improve the speed of cut-off frequency adjustment. | 07-14-2011 |
Chang-Sik Yoo, Seoul-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080225606 | DATA OUTPUT CIRCUIT AND METHOD IN DDR SYNCHRONOUS SEMICONDUCTOR DEVICE - Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted into DDR data and are then serially output. By moving data in this manner, embodiments of the invention can reduce the number of necessary control signals by as much as 50% over conventional data output circuits. | 09-18-2008 |
Chang-Sik Yoo, Seoulsi KR
| Patent application number | Description | Published |
|---|---|---|
| 20090195316 | RE-CONFIGURABLE LOW NOISE AMPLIFIER UTILIZING FEEDBACK CAPACITORS - A re-configurable low noise amplifier utilizing feedback capacitors is disclosed. The low noise amplifier has output transistors, capacitor switch cells, and capacitance distributors all in an output terminal. The output transistors are for controlling selection of a specific frequency band in a wide band of frequencies. The capacitor switch cells are for adjusting a harmonic frequency for the specific frequency band. The capacitance distributor is for determining an amount of gain, and according to the gain, an output impedance feeds back to an input terminal of the low noise amplifier for input matching. Since the output terminal is at high impedance and suitable for a wide band of frequencies, input matching not only makes the low noise amplifier applicable to kinds of wireless communication standards, but also fulfills high gain and low noise figure. | 08-06-2009 |
Chang-Sik Yoo, Bucheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090219204 | DUAL MODE SATELLITE SIGNAL RECEIVER AND METHOD THEREOF - A dual mode satellite signal receiver capable of supporting at least two global navigation satellite systems and a satellite signal receiving method are provided. The dual mode satellite signal receiver comprises a frequency synthesizer for generating a local oscillator signal based on a reference frequency; a mixer for mixing the local oscillator signal with a satellite signal and outputting the mixed signal as a signal of an intermediate frequency band; a first filter for filtering the signal output from the mixer to reject an image signal and output only an actual signal; a second filter for filtering the actual signal to output only a predetermined bandwidth according to a positioning mode; and an amplifier for amplifying the second filter output signal to a predetermined level and outputting the amplified signal. | 09-03-2009 |