Patent application number | Description | Published |
20090015488 | HIGH DIELECTRIC ANTENNA SUBSTRATE AND ANTENNA THEREOF - A high dielectric antenna substrate includes a first dielectric layer having a first dielectric constant, and a second dielectric layer having a second dielectric constant. The second dielectric layer is formed on one surface of the first dielectric layer. The second dielectric constant is lower than the first dielectric constant. Furthermore, a first metal layer and a second metal layer are optionally formed on the same surface or two surfaces of the first dielectric layer to compose a capacitor. | 01-15-2009 |
20090051469 | MULTI-FUNCTIONAL COMPOSITE SUBSTRATE STRUCTURE - A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal. | 02-26-2009 |
20100226112 | MIRROR IMAGE SHIELDING STRUCTURE - A mirror image shielding structure is provided, which includes an electronic element and a ground shielding plane below the electronic element. The shape of the ground shielding plane is identical to the projection shape of the electronic element, and the horizontal size of the ground shielding plane is greater than or equal to that of the electronic element. Thus, the parasitic effect between the electronic element and the ground shielding plane is effectively reduced, and the vertical coupling effect between electronic elements is also reduced. Furthermore, the vertical impact on the signal integrity of the embedded elements caused by the layout of the transmission lines is prevented. | 09-09-2010 |
20100259338 | High frequency and wide band impedance matching via - A high frequency and wide band impedance matching via is provided, applicable to multi-layer printed circuit boards, for example. The multi-layer circuit board may include several signal transmission traces, several ground layers, signal transmission vias and ground vias. The signal transmission traces and the ground layers may be sited on different circuit layers, and each signal transmission trace may be opposite to one of the ground layers. The signal transmission vias may be connected between the signal transmission traces. The ground vias may be connected between the ground layers. The ground vias may be opposite to the signal transmission vias, and the ground vias corresponding to the signal transmission vias may be sited to stabilize the characteristic impedance of the transmission traces. | 10-14-2010 |
Patent application number | Description | Published |
20110169139 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposite second surface. A through hole is formed on the first surface, extending from the first surface to the second surface. A conductive trace layer is formed on the first surface and in the through hole. A buffer plug is formed in the through hole and a protection layer is formed over the first surface and in the through hole. | 07-14-2011 |
20110175221 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package contains a semiconductor substrate having a chip. A packaging layer is disposed over the semiconductor substrate. A spacer is disposed between the semiconductor substrate and the packaging layer, wherein a side surface consisting of the semiconductor substrate, the spacer and the packaging layer has a recess section. The method includes forming a plurality of spacers between a plurality of chips of a semiconductor wafer and a packaging layer, wherein each spacer corresponding to each chip is separated from each other and the spacer is shrunk inward from an edge of the chip to form a recess section and dicing the semiconductor wafer along a scribe line between any two adjacent chips to form a plurality of chip packages. | 07-21-2011 |
20130312246 | METHOD FOR SUPPORTING SEMICONDUCTOR WAFER AND WAFER SUPPORTING ASSEMBLY - A method for supporting a semiconductor wafer includes providing a device wafer to a magnetizable ring, providing a magnetizable carrier to the device wafer, and magnetizing the magnetizable ring and the magnetizable carrier to form a magnetized clamp having a magnetized ring and magnetized carrier. The magnetized clamp securely clamps the device wafer therebetween. | 11-28-2013 |
20130313691 | THINNED WAFER AND FABRICATING METHOD THEREOF - A thinning method of a wafer is provided. The method includes the following steps. First, a wafer having a first surface, a second surface, and a side surface is provided, and the side surface is connected between the first surface and the second surface. At least one semiconductor device is formed on the first surface. Then, an anisotropy etching process is performed to the second surface with a mask to remove portions of the wafer while remaining the side surface thereby forming a number of grooves in the second surface and at least one reinforcing wall between the grooves. As a result, a thinned wafer is obtained. | 11-28-2013 |
20140017854 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package contains a semiconductor substrate having a chip. A packaging layer is disposed over the semiconductor substrate. A spacer is disposed between the semiconductor substrate and the packaging layer, wherein a side surface consisting of the semiconductor substrate, the spacer and the packaging layer has a recess section. The method includes forming a plurality of spacers between a plurality of chips of a semiconductor wafer and a packaging layer, wherein each spacer corresponding to each chip is separated from each other and the spacer is shrunk inward from an edge of the chip to form a recess section and dicing the semiconductor wafer along a scribe line between any two adjacent chips to form a plurality of chip packages. | 01-16-2014 |
20140319693 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor device is disclosed. Provided is a substrate having at least one MOS device, at least one metal interconnection and at least one MOS device formed on a first surface thereof. A first anisotropic etching process is performed to remove a portion of the substrate from a second surface of the substrate and thereby form a plurality of vias in the substrate, wherein the second surface is opposite to the first surface. A second anisotropic etching process is performed to remove another portion of the substrate from the second surface of the substrate and thereby form a cavity in the substrate, wherein the remaining vias are located below the cavity. An isotropic etching process is performed to the cavity and the remaining vias. | 10-30-2014 |
Patent application number | Description | Published |
20150129414 | PROCESS KIT OF PHYSICAL VAPOR DEPOSITION CHAMBER AND FABRICATING METHOD THEREOF - A physical vapor deposition (PVD) chamber, a process kit of a PVD chamber and a method of fabricating a process kit of a PVD chamber are provided. In various embodiments, the PVD chamber includes a sputtering target, a power supply, a process kit, and a substrate support. The sputtering target has a sputtering surface that is in contact with a process region. The power supply is electrically connected to the sputtering target. The process kit has an inner surface at least partially enclosing the process region, and a liner layer disposed on the inner surface. The substrate support has a substrate receiving surface, wherein the liner layer disposed on the inner surface of the process kit has a surface roughness (Rz), and the surface roughness (Rz) is substantially in a range of 50-200 μm. | 05-14-2015 |
20150147892 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE, AND SOLID PRECURSOR DELIVERY SYSTEM - A method for fabricating a semiconductor structure is provided, including: providing a solid precursor having a first average particle size; solving the solid precursor in an organic solvent into an intermediate; recrystallizing the intermediate to form solid granules, wherein the solid granules has a second average particle size larger than the first average particle size; vaporizing the solid granules to form a film-forming gas; and depositing the film-forming gas on a substrate to form a resistance film. A method for modifying a resistance film source in a semiconductor fabrication and a solid precursor delivery system are also provided. The method for fabricating a semiconductor structure in the present disclosure can remove small particles or ultra-small particles from solid precursor, and does not need extra time to dump cracked solid precursor. | 05-28-2015 |
20150183080 | APPARATUS AND METHOD FOR CHEMICAL MECHANICAL POLISHING - An apparatus for chemical mechanical polishing includes a wafer carrier, a first electrode, a rotatable pedestal, a second electrode, and an electric current detector. The first electrode is disposed at the wafer carrier. The rotatable pedestal is positioned opposite to the wafer carrier in order to perform a polishing operation with the wafer carrier accordingly. The second electrode is disposed at the rotatable pedestal and electrically coupled to the first electrode in order to form a circuit loop. The electric current detector is between the first electrode and the second electrode. | 07-02-2015 |
20150371847 | METHOD FOR CONTROLLING SEMICONDUCTOR DEPOSITION OPERATION - The present disclosure provides a method for controlling a semiconductor deposition operation. The method includes (i) identifying a first target lifetime in a physical vapor deposition (PVD) system; (ii) inputting the first target lifetime into a processor; (iii) outputting, by the processor, a plurality of first operation parameters according to a plurality of compensation curves; and (iv) performing the first operation parameters in the PVD system. The first operation parameters includes, but not limited to, an RF power tuning, a DC voltage tuning, a target to chamber pedestal spacing tuning, an AC bias tuning, an impedance tuning, a reactive gas flow tuning, an inert gas flow tuning, a chamber pedestal temperature tuning, or a combination thereof. | 12-24-2015 |
Patent application number | Description | Published |
20100080717 | Fan motor for combustion-powered tool - A fan motor is adapted to be mounted in a combustion-powered tool. The combustion-powered tool has a housing. The fan motor includes a fan unit, a motor for driving the fan unit, a vibration-absorbing unit, and a clamping unit. The vibration-absorbing unit includes a rigid support that is adapted to be mounted fixedly in the housing of the combustion-powered tool, and an elastic member sleeved over the motor and molded on the rigid support such that the rigid support is disposed around the elastic member. The elastic member is disposed between the rigid support and the motor for absorbing vibrations generated by the motor. The clamping unit includes at least one clamping member sleeved over the elastic member for clamping and retaining the elastic member on the motor. | 04-01-2010 |
20100237127 | OSCILLATION REDUCING SUSPENSION DEVICE FOR A FAN MOTOR OF A COMBUSTION-POWERED TOOL - An oscillation reducing suspension device for a fan motor of a combustion-powered tool includes a rigid axial-play setting unit mounted on an upper major surface of a cylinder head, and having upper and lower limit defining members that are spaced apart from each other by an axial play route, a suspending mount configured to keep the fan motor oriented in a rotary axis, and having a lug which extends radially into the axial play route to divide the axial play route into proximate and distal regions, and an elastomeric damper unit having upper and lower damping members respectively disposed in the distal and proximate regions. By virtue of the rigid mount supporting the fan motor, and the resilient damper unit coupling the mount and the cylinder head, the fan motor is firmly secured to the cylinder head, and axial oscillation of the fan motor is reduced. | 09-23-2010 |
20120037682 | DUAL SAFETY COMBUSTION POWERED TOOL DEVICE - A dual safety combustion powered tool device includes a push member disposed to be pressed against a targeted surface to bring a lever to turn to be closer to an actuating unit. A trigger body is pulled to move the actuating unit so as to permit an actuating region to abut against the lever and to turn the actuating unit to an orientation where an actuating region is engageable with an ignition switch. Subsequently, a further movement of the trigger body to a final-stage position permits the actuating region to switch on the ignition switch so as to ignite combustion for initiation of a stroke movement of a driver blade. With such construction, undesired firing of the combustion powered tool device can be avoided. | 02-16-2012 |
20130242530 | STATUS INDICATING DEVICE FOR A POWER NAIL GUN - A status indicating device for a power nail gun includes a trigger adapted to be disposed on a gun body and having at least one transparent portion, and a light emitting module adapted to be disposed between the gun body and the trigger for emitting light through the transparent portion. | 09-19-2013 |
20140319400 | METERING VALVE - A metering valve includes a valve main body consisting of a body and a cover, a sliding rod and an elastic member. The body has a positioning hole, a metering chamber, a containing space, and two sealing pads disposed on two end portions of the metering chamber. The containing space is for assembling the gas cylinder A groove is disconnected with the positioning hole, the metering chamber and the containing space. The sliding rod has two ends, wherein a gas channel is formed from one end toward an inner of the sliding rod, the sliding rod has a flange and a through hole, the through hole under the flange is for connecting the gas channel, and the sliding rod blocks a gas from the metering chamber by cooperating with the sealing pads. The elastic member in the groove is connected to the flange and the groove. | 10-30-2014 |
20140367441 | COMBUSTION-TYPE POWER TOOL - In a combustion-type power tool, when a safety unit is pressed against a workpiece to cause a valve sleeve to close a combustion chamber, a power region of a lever is actuated to permit a weight region of the lever to displace a holding member holding a fuel canister from a normal position to a pressed position. When the holding member is in the pressed position, a valve stem of the fuel canister is forced into pressing engagement with an intake port of a fuel canister actuation unit to permit delivery of a measured dose of fuel to the combustion chamber through the intake port. | 12-18-2014 |
20150060514 | FIRING-OPERATION TOTALIZING DEVICE FOR A GAS NAIL GUN - A firing-operation totalizing device for a gas nail gun includes two pressure areas, a pressure feedback unit mounted in a body, and an electric control unit. The pressure areas are constituted by an interior of a combustion chamber and an interior of a cylinder body. The pressure feedback unit outputs a pressure signal in response to each pressure change of at least one of the pressure areas. The electric control unit includes a control circuit that totalizes the number of the firing operations based on the pressure signals received thereby. As such, the totalized number of the firing operations is increased only when a pressure change of the at least one of the pressure areas occurs due to an explosion to totalize accurately the number of effective firing operations. | 03-05-2015 |
Patent application number | Description | Published |
20140377954 | METHOD AND APPARATUS FOR IMPROVING CMP PLANARITY - Provided is a method of planarizing a semiconductor device. A dielectric layer is formed over a substrate. A plurality of openings is formed in the dielectric layer. The openings have varying distribution densities. The openings are filled with a metal material. A first chemical-mechanical-polishing (CMP) process is performed to remove portions of the metal material over the dielectric layer. Thereafter, a sacrificial layer is formed over the dielectric layer and the metal material. The sacrificial layer has a planar surface. The sacrificial layer is formed through one of: a spin-on process or a flowable chemical vapor deposition (FCVD) process. A second CMP process is then performed to remove the sacrificial layer and portions of the dielectric layer and the metal material therebelow. The second CMP process uses a slurry configured to have a substantially similar polishing selectivity between the sacrificial layer, the dielectric layer, and the metal material. | 12-25-2014 |
20150174727 | CARRIER HEAD HAVING RETAINER RING, POLISHING SYSTEM INCLUDING THE CARRIER HEAD AND METHOD OF USING THE POLISHING SYSTEM - A carrier head includes a housing configured to enclose a wafer, wherein the housing includes a retaining ring recess. The carrier head includes a retaining ring positioned in the retaining ring recess, the retaining ring configured to surround the wafer. The retaining ring has a hardness ranging from about 5 shore A to about 80 shore D. A method of using a polishing system includes securing a wafer in a carrier head. The carrier head includes a housing enclosing the wafer, wherein the housing includes a retaining ring recess. The carrier head includes a retaining ring in the retaining ring recess. The retaining ring has a hardness ranging from about 5 shore A to about 80 shore D. The method includes pressing the wafer against a polishing pad, and moving at least one of the carrier head or the polishing pad relative to the other. | 06-25-2015 |
20150235858 | WAFER BACK-SIDE POLISHING SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE MANUFACTURING PROCESSES - A wafer polishing process includes polishing a central area on the back side of a wafer, polishing a peripheral area on the back side of the wafer, buffing the central area, and buffing the peripheral area. The process can significantly reduce scratch-related wafer breakage, can correct focus spots on wafers, and can replace cleaning processes that use chemical etchants. Polishing and buffing can include polishing and buffing the bevel region. Further improvements include polishing with abrasive pads having a soft backing, polishing or buffing with pads having relatively soft abrasive particles, polishing or buffing with abrasive pads made from abrasive particles that have been sorted and selected for regularity of shape, irrigating the surface being polished or buffed with an aqueous solution that includes a friction-reducing agent, and buffing with abrasive pads having 20k or finer grit or non-abrasive pads. | 08-20-2015 |
20150263132 | BARC-ASSISTED PROCESS FOR PLANAR RECESSING OR REMOVING OF VARIABLE-HEIGHT LAYERS - An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a bottom anti-reflective coating (BARC), baking to induce cross-linking in the BARC, CMP to remove a first portion of the BARC and form a planar surface, then plasma etching to effectuate a planar recessing of the BARC. The plasma etching can have a low selectivity between the BARC and the material being recessed, whereby the BARC and the material are recessed simultaneously. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The method can be particularly effective when an abrasive used during CMP forms ester linkages with the BARC. | 09-17-2015 |
20150306737 | CHEMICAL MECHANICAL POLISHING PAD - The present disclosure relates to a radiance decomposable CMP pad, and an associated method to refresh the CMP pad. In some embodiments, the CMP pad has a polymer layer and some macro pores disposed therein. A monomer of the polymer layer has a photoactive compound unit. | 10-29-2015 |
20160099157 | BARC-ASSISTED PROCESS FOR PLANAR RECESSING OR REMOVING OF VARIABLE-HEIGHT LAYERS - The present disclosure provides a method of manufacturing an integrated circuit device in some embodiments. In the method, a semiconductor substrate is processed through a series of operations to form a topographically variable surface over the semiconductor substrate. The topographically variable surface varies in height across the semiconductor substrate. A polymeric bottom anti-reflective coating (BARC) is provided over the topographically variable surface. Chemical mechanical polishing is performed to remove a first portion of the BARC, and etching effectuates a top-down recessing of the BARC. | 04-07-2016 |