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Chang, Shanghai
Clifford C. Chang, Shanghai JP
| Patent application number | Description | Published |
|---|---|---|
| 20110174410 | FIBER-REINFORCED THERMOPLASTIC PIPE - Disclosed is a reinforced thermoplastic pipe, comprising a thermoplastic polymer inner tube, a thermoplastic polymer outer tube and a reinforcing fabric between the thermoplastic polymer inner tube and the thermoplastic polymer outer tube. The reinforcing fabric comprises thermosettable thermoplastic polymer weft yarns and unidirectionally woven warp yarns. The warp yarns are twisted into twisted cords. Disclosed is also a process of making the reinforced thermoplastic pipe. | 07-21-2011 |
Hsiang-Li Chang, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20100037071 | Using Internet to control delivery of power to a set of remote loads(devices) - This application describes an original concept, model, design, method and components of controlling delivery of power to one or many loads through the internet. It supports global power management as a service model. This service can be optimized with different criteria including but not limited to priority, efficiency, savings, costs, performance, season and time of the day . . . and this service can be implemented by computer software. The design consists of (i) Internet and its distributed data centers/computer clusters/databases/application software/Internet service provider (ii) a new type of web-enabled power cycler (iii) one or more gateway and another new type of wireless PAN/LAN/WAN-enabled power cyclers (iv) devices capable of accessing Internet for remote control. | 02-11-2010 |
Jain Guang Chang, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20100190329 | METHOD AND STRUCTURE FOR PERFORMING A CHEMICAL MECHANICAL POLISHING PROCESS - A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a doped dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material. | 07-29-2010 |
Jiang Guang Chang, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20100248468 | METHOD AND STRUCTURE FOR PERFORMING A CHEMICAL MECHANICAL POLISHING PROCESS - A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a photo resist material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material. | 09-30-2010 |
Jian Guang Chang, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20100227464 | METHOD AND STRUCTURE FOIR PERFORMING A CHEMICAL MECHANICAL POLISHING PROCESS - A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method subjects the second upper surface region to a chemical mechanical polishing process to remove the first elevated region, the second elevated region, and the third elevated region to cause formation of a substantially planarized second polysilicon layer free from the fill material. | 09-09-2010 |
| 20100227465 | METHOD AND STRUCTURE FOR PERFORMING A CHEMICAL MECHANICAL POLISHING PROCESS - A method for fabricating flash memory devices, e.g., NAND, NOR, is provided. The method includes providing a semiconductor substrate. The method includes forming a second polysilicon layer overlying a plurality of floating gate structures to cause formation of an upper surface provided on the second polysilicon layer. The upper surface has a first recessed region and a second recessed region. The method includes depositing a dielectric material overlying the upper surface to fill the first recessed region and the second recessed region to form a second upper surface region and cover a first elevated region, a second elevated region, and a third elevated region. The method forms at least one dielectric spacer within the first recessed region and at least one dielectric spacer within the second recessed region to form a resulting surface region, and subjects the resulting surface region to a chemical mechanical polishing process to cause formation of a substantially planarized second polysilicon layer free from the dielectric material. | 09-09-2010 |
Jicheng Chang, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20080242827 | Method for producing omni-meta aromatic polysulfonamide fiber - The invention relates to a method of preparing omni-meta aromatic polysulfonamide fiber which comprises three steps of preparing spinning dope, wet spinning and post treating. The said step of preparing spinning dope comprises the following steps: (1) dissolving 3,3′-diaminodiphenyl sulphone in a polar organic solvent and cooling it to −20˜20° C.; (2) adding m-phthaloyl chloride of the same mole of the 3,3′-diaminodiphenyl sulphone to carry out a polymerization reaction; (3) then adding an inorganic base of the same mole of 3,3′-diaminodiphenyl sulphone to neutralize the hydrogen chloride produced during the polymerization reaction. The spinning dope thus prepared has a polymer solid content of 10%-20%. The fiber prepared according to the method in the present invention has a greatly improved crimpability, and evidently increased elongation at break comparing with the conventional aromatic polysulfonamide fiber, so that the spinnability of resultant yarn is improved. | 10-02-2008 |
Jung-Che Chang, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20100001738 | System and Method for Conducting Accelerated Soft Error Rate Testing - An apparatus for a user to conduct an accelerated soft error test (ASER) on a semiconductor sample is provided. The apparatus comprises a first component for holding the radiation source, where the radiation source may be either an alpha-particle or neutron-particle source. The apparatus comprises a second component for holding the semiconductor sample, where the semiconductor sample may be either a silicon wafer or semiconductor chip. The apparatus comprises a connecting assembly for placing the first component and the second component relative to each other at a plurality of positions that subject the semiconductor sample to a radiation stress from the radiation source at a plurality of stress efficiencies. Among the benefits provided are improved repeatability and credibility of ASER tests and reduced radiation exposures to operators of ASER tests. | 01-07-2010 |
Lee Chang, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20090200564 | Method and Structure for Fabricating Smooth Mirrors for Liquid Crystal on Silicon Devices - A method for fabricating a liquid crystal on silicon display device. The method includes providing a substrate, e.g., silicon wafer. The method includes forming a transistor layer overlying the substrate. Preferably, the transistor layer has a plurality of MOS devices therein. The method includes forming an interlayer dielectric layer (e.g., BPSG, FSG) overlying the transistor layer. The method includes planarizing the interlayer dielectric layer and forming a sacrificial layer (e.g., bottom antireflective coating, polymide, photoresist, polysilicon) overlying the planarized interlayer dielectric layer. The method includes forming a plurality of recessed regions within a portion of the interlayer dielectric layer through the sacrificial layer while other portions of the interlayer dielectric layer remain intact. Preferably, lithographic techniques are used for forming the recessed regions. The method includes forming an aluminum layer (or other reflective layer or multilayers) to fill the recessed regions and overlying remaining portions of the sacrificial layer and selectively removing the aluminum layer overlying portions of the sacrificial layer to form a plurality of electrode regions corresponding to each of the recessed regions. | 08-13-2009 |
Ningjuan Chang, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20120092994 | TRAFFIC BEARER MAPPING METHOD AND COMMUNICATION DEVICE - Embodiments of the present invention provide a traffic bearer mapping method and a communication device. The traffic bearer mapping method includes: obtaining attribute information of a traffic data flow of a user; selecting a relay transmission tunnel according to the attribute information of the traffic data flow of the user; and mapping the received traffic data flow to the relay transmission tunnel for transmission, where the relay transmission tunnel includes a relay link radio bearer Un RB or a bearer including the Un RB. According to the embodiments of the present invention, transmission of a traffic data flow in an LTE-A network after a relay node is introduced into is implemented, thereby ensuring quality of service of multi-service. | 04-19-2012 |
Richard Rugin Chang, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20120132941 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides a light emitting device and a method for manufacturing a light emitting device. The light emitting device includes a base, an LED inversely mounted on the base. The LED includes an LED chip connected to the base and a buffer layer located on the LED. The buffer layer includes a plurality of depressions with complementary pyramid structure on a surface of the buffer layer not face the LED, the surface being a light-exiting surface of the LED. The buffer layer is made from silicon carbide. The light emitting device has a large area of the light-exiting surface and provides a reflecting film on a base, thus improving the luminous efficiency of the light emitting device. Inversely mounting mode is adopt, which is easy to implement. | 05-31-2012 |
Ryan Chang, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20110053661 | MOBILE COMMUNICATION DEVICE WITH ERGONOMIC FEATURE - A mobile communication device with an ergonomic feature comprises a housing, a display unit, a first key module, and a second key module. The display unit is arranged on a lower part of one face of the housing, and the first key module is arranged on the housing on the same face as the display unit to locate closely above the display unit. The first key module comprises a plurality of upside keys which are arrayed into a laterally symmetric hexagonal configuration. The second key module comprises a plurality of lateral keys located on one of two opposite lateral surfaces of the housing. The keys of the two key modules are so arranged on the housing that either a right-handed or a left-handed user can conveniently operate the keys not only with a thumb but also the other four fingers while holding the device with one single hand. | 03-03-2011 |
Suolin Chang, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20110305307 | NETWORK NODE, COMMUNICATION SYSTEM, AND METHOD FOR TRANSMITTING CLOCK PACKET THROUGH TUNNEL - A network node, a communication system, and a method for transmitting a clock packet through a tunnel are disclosed. The method includes: encapsulating a tunnel ingress clock packet received at an ingress of a tunnel in an encapsulation mode corresponding to the tunnel, and performing clock correction for the encapsulated clock packet; and sending the corrected clock packet to an egress of the tunnel. The network node for processing a clock packet includes an encapsulating module and a sending module. The communication system includes the network node for processing a clock packet, and further includes an intra-tunnel network node and a tunnel egress network node. According to the present invention, a clock packet is re-encapsulated and transmitted through a tunnel. In the subsequent process of transmitting the clock packet transparently, the node itself serves as a clock reference point, and all network nodes do not need to synchronize time absolutely. | 12-15-2011 |
Tsung Chih Chang, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20080290669 | Device For Controlling a Door - A device for controlling a door, the device having: a body; an electromagnet arranged to generate a magnetic field for retaining the door; a coupling that couples the electromagnet to the body, the coupling being arranged to allow a movement of the electromagnet relative to the body; and a current supply that is arranged to supply the electromagnet with a current. The current supply is arranged to detect the movement of the electromagnetic and to cease supplying the current at a predetermined instant after detecting the movement of the electromagnet. | 11-27-2008 |
| 20090174553 | ELECTROMAGNETIC DOOR LOCK - An electromagnetic door lock is described which includes at least two external generally planar surfaces and light emitting means; the light emitting means indicates the status of the lock and is arranged to emit light from the at least two external surfaces. | 07-09-2009 |
Venson Chang, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20110084718 | Burn-In Testing System - The present invention discloses a burn-in testing system including a burn-in board and a burn-in testing apparatus, the burn-in board including: a first interface component, adapted to connect with the burn-in testing apparatus for signal input and/or output between the burn-in board and the burn-in testing apparatus; and a second interface component, adapted to connect with a device under test for signal input and/or output between the burn-in board and the device, wherein the burn-in testing system further includes a pin matching unit flexibly connected with the burn-in board and adapted to adjust signal connection relationship between the first interface component and the second interface component according to a pin description of the device. By using the invention, burn-in tests of various devices having the same number of pins and different pin descriptions can be performed using the same burn-in board, which is compatible with existing burn-in boards, thereby improving production efficiency and reducing production costs. | 04-14-2011 |
Zhigang Chang, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20120005242 | DIMENSION-BASED RELATION GRAPHING OF DOCUMENTS - Described herein is a technology for visualizing data. In accordance with some implementations, dimension metadata is automatically extracted from multiple documents. The extracted dimension metadata may be used to populate one or more relation dimensions. Based on the dimension metadata, one or more relations between the documents are determined along the one or more relation dimensions. A relation graph is presented to represent the documents interconnected by the one or more relations. | 01-05-2012 |
Zhongyuan Chang, Shanghai CN
| Patent application number | Description | Published |
|---|---|---|
| 20090160487 | Phase and frequency detector with zero static phase error - A method and circuit for phase and frequency detection having zero static phase error for use in a phase-locked loop system is presented. The phase and frequency detector utilizes a first phase and frequency detector configured to generate first and second pulsed PFD signals. Pulse blocking circuitry is utilized to provide first and second output signals based on the first and second pulsed signals respectively, wherein a time period when both first and second output signals are asserted is substantially reduced from a time period when both first and second pulsed signals are asserted. By reducing the time the first and second output signals are simultaneously asserted, the effects of charge pump current source mismatch are minimized and static phase error is reduced. | 06-25-2009 |
| 20100007641 | Voltage-mode line driving circuit having adaptive impedance matching - A voltage-mode line driving circuit is provided. The voltage-mode line driving circuit includes a driving circuit, the driving circuit receiving, as an input signal, a feedback signal, and outputting an output signal. The voltage-mode line driving signal also includes an adaptive tuning circuit coupled to the driving circuit, the adaptive tuning circuit receiving as input signals the feedback signal and the output signal and adaptively outputting a modifying signal to the driving circuit which modifies the feedback signal. | 01-14-2010 |
| 20100045389 | RING OSCILLATOR - A ring oscillator is disclosed for generating one or more clock signals. In some embodiments, the ring oscillator includes a first set of n series coupled inverters, a second set of n series coupled inverters, a first reset switch configured to couple a last inverter of the first set of inverters to a first inverter of the second set of inverters and to generate a first signal edge, a second reset switch configured to couple a last inverter of the second set of inverters to a first inverter of the first set of inverters, and a cross-coupling circuit coupled between an output of an inverter of the first set of inverters to a corresponding output of an inverter of the second set of inverters. In some embodiments, 2n clock signals separated in phase by 360°/2n may be generated. | 02-25-2010 |