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Chang, Saratoga
Asia Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100147294 | DEVICES AND METHODS TO MAINTAIN THE PATENCY OF AN OPENING RELATIVE TO PARENCHYMAL TISSUE OF THE LUNG - A mechanical device and/or chemical process is utilized to maintain luminal patency in conduits or other devices implanted in the lung or lungs of a patient. The mechanical device and/or chemical process ensures that air flows freely through a conduit implanted through an anastomosis into a lung. The device is suitable for use in conjunction with ventilation bypass treatments for chronic obstructive pulmonary disease. | 06-17-2010 |
| 20100147295 | DEVICES AND METHODS TO CREATE AND MAINTAIN THE PATENCY OF AN OPENING RELATIVE TO PARENCHYMAL TISSUE OF THE LUNG - A mechanical device and/or chemical process is utilized to maintain luminal patency in conduits or other devices implanted in the lung or lungs of a patient. The mechanical device and/or chemical process ensures that air flows freely through a conduit implanted through an anastomosis into a lung. The device is suitable for use in conjunction with ventilation bypass treatments for chronic obstructive pulmonary disease. | 06-17-2010 |
Chi Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090061631 | GATE REPLACEMENT WITH TOP OXIDE REGROWTH FOR THE TOP OXIDE IMPROVEMENT - Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide. | 03-05-2009 |
| 20100283100 | SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION - A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures. | 11-11-2010 |
| 20110175158 | DUAL CHARGE STORAGE NODE MEMORY DEVICE AND METHODS FOR FABRICATING SUCH DEVICE - A dual node memory device and methods for fabricating the device are provided. In one embodiment the method comprises forming a layered structure with an insulator layer, a charge storage layer, a buffer layer, and a sacrificial layer on a semiconductor substrate. The layers are patterned to form two spaced apart stacks and an exposed substrate portion between the stacks. A gate insulator and a gate electrode are formed on the exposed substrate, and the sacrificial layer and buffer layer are removed. An additional insulator layer is deposited overlying the charge storage layer to form insulator-storage layer-insulator memory storage areas on each side of the gate electrode. Sidewall spacers are formed at the sidewalls of the gate electrode overlying the storage areas. Bit lines are formed in the substrate spaced apart from the gate electrode, and a word line is formed that contacts the gate electrode and the sidewall spacers. | 07-21-2011 |
Chia-Pu Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110157682 | DISPLAY CELL STRUCTURE AND ELECTRODE PROTECTING LAYER COMPOSITIONS - The invention is directed to compositions of display cell structure and electrode protecting layers for improving the performance of display devices. The composition comprises a polar oligomeric or polymeric material having a glass transition temperature below about 100° C., and the resulting display cells or electrode protecting layer have an average crosslinking density of below about 1 crosslink point per 80 Dalton molecular weight. | 06-30-2011 |
Chorng-Ping Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090189201 | INWARD DIELECTRIC SPACERS FOR REPLACEMENT GATE INTEGRATION SCHEME - Inward dielectric spacers for a replacement gate integration scheme are described. A semiconductor device is fabricated by first providing a substrate having thereon a placeholder gate electrode disposed in a dielectric layer. The placeholder gate electrode is removed to from a trench in the dielectric layer. A pair of dielectric spacers is then formed adjacent to the sidewalls of the trench. Finally, a gate electrode is formed in the trench and adjacent to the pair of dielectric layers. | 07-30-2009 |
| 20090311635 | DOUBLE EXPOSURE PATTERNING WITH CARBONACEOUS HARDMASK - Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance. | 12-17-2009 |
Edward Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100328468 | Adaptive Video Processing Circuitry and Techniques - Video processing circuitry to adaptively process input video data which corresponds to a plurality of video frames of a selected channel which is one of a plurality of channels of a broadcast spectrum. In one aspect, the video processing circuitry includes spatial adaption circuitry to generate and output spatially adapted video data corresponding to the plurality of video frames, temporal adaption circuitry to generate and output temporally adapted video data corresponding to the plurality of video frames, and video manipulation circuitry, coupled to the spatial adaption circuitry and the temporal adaption circuitry, to generate output video data corresponding to the plurality of video frames, using the input video data, the spatially adapted video data and the temporally adapted video data. Methods of adaptively processing input video data which corresponds to a plurality of video frames of a selected channel which is one of a plurality of channels of a broadcast spectrum are also disclosed. | 12-30-2010 |
Ellis Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090043527 | COMPUTER-IMPLEMENTED METHODS, CARRIER MEDIA, AND SYSTEMS FOR GENERATING A METROLOGY SAMPLING PLAN - Various computer-implemented methods, carrier media, and systems for generating a metrology sampling plan are provided. One computer-implemented method for generating a metrology sampling plan includes identifying one or more individual defects that have one or more attributes that are abnormal from one or more attributes of a population of defects in which the individual defects are included. The population of defects is located in a predetermined pattern on a wafer. The method also includes generating the metrology sampling plan based on results of the identifying step such that one or more areas on the wafer in which the one or more identified individual defects are located are sampled during metrology. | 02-12-2009 |
| 20090257645 | METHODS AND SYSTEMS FOR DETERMINING A DEFECT CRITICALITY INDEX FOR DEFECTS ON WAFERS - Various methods and systems for determining a defect criticality index (DCI) for defects on wafers are provided. One computer-implemented method includes determining critical area information for a portion of a design for a wafer surrounding a defect detected on the wafer by an inspection system based on a location of the defect reported by the inspection system and a size of the defect reported by the inspection system. The method also includes determining a DCI for the defect based on the critical area information, a location of the defect with respect to the critical area information, and the reported size of the defect. | 10-15-2009 |
| 20090297019 | METHODS AND SYSTEMS FOR UTILIZING DESIGN DATA IN COMBINATION WITH INSPECTION DATA - Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium. | 12-03-2009 |
| 20110170091 | INSPECTION GUIDED OVERLAY METROLOGY - Inspection guided overlay metrology may include performing a pattern search in order to identify a predetermined pattern on a semiconductor wafer, generating a care area for all instances of the predetermined pattern on the semiconductor wafer, identifying defects within generated care areas by performing an inspection scan of each of the generated care areas, wherein the inspection scan includes a low-threshold or a high sensitivity inspection scan, identifying overlay sites of the predetermined pattern of the semiconductor wafer having a measured overlay error larger than a selected overlay specification utilizing a defect inspection technique, comparing location data of the identified defects of a generated care area to location data of the identified overlay sites within the generated care area in order to identify one or more locations wherein the defects are proximate to the identified overlay sites, and generating a metrology sampling plan based on the identified locations. | 07-14-2011 |
| 20110172804 | Scanner Performance Comparison And Matching Using Design And Defect Data - A system and method of matching multiple scanners using design and defect data are described. A golden wafer is processed using a golden tool. A second wafer is processed using a second tool. Both tools provide focus/exposure modulation. Wafer-level spatial signatures of critical structures for both wafers can be compared to evaluate the behavior of the scanners. Critical structures can be identified by binning defects on the golden wafer having similar patterns. In one embodiment, the signatures must match within a certain percentage or the second tool is characterized as a “no match”. Reticles can be compared in a similar manner, wherein the golden and second wafers are processed using a golden reticle and a second reticle, respectively. | 07-14-2011 |
| 20110187848 | COMPUTER-IMPLEMENTED METHODS, COMPUTER-READABLE MEDIA, AND SYSTEMS FOR CLASSIFYING DEFECTS DETECTED IN A MEMORY DEVICE AREA ON A WAFER - Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer are provided. | 08-04-2011 |
Hong Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110049618 | FABRICATION OF TRENCH DMOS DEVICE HAVING THICK BOTTOM SHIELDING OXIDE - Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure. | 03-03-2011 |
| 20110095361 | MULTIPLE LAYER BARRIER METAL FOR DEVICE COMPONENT FORMED IN CONTACT TRENCH - A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer. | 04-28-2011 |
Jean C. Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090281611 | SLIDING RESTRAINT STENT DELIVERY SYSTEMS - Medical device and methods for delivery or implantation of prostheses within hollow body organs and vessels or other luminal anatomy are disclosed. The subject technologies may be used in the treatment of atherosclerosis in stenting procedures. For such purposes, a self-expanding stent may be deployed in connection with an angioplasty procedure with a sliding restraint based delivery system adapted for simplified use. In the system, the sliding restraint is sized, in coordination with a fixed sleeve accepting a core wire to actuate the restraint to effect an anchoring function with the sleeve so that the stent is not inadvertently advanced during deployment. | 11-12-2009 |
Jia-Hwang Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090185410 | METHOD AND SYSTEM FOR PROVIDING SPIN TRANSFER TUNNELING MAGNETIC MEMORIES UTILIZING UNIDIRECTIONAL POLARITY SELECTION DEVICES - A magnetic memory cell and a magnetic memory incorporating the cell are described. The magnetic memory cell includes at least one magnetic element and a plurality of unidirectional polarity selection devices. The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The unidirectional polarity selection devices are connected in parallel and such that they have opposing polarities. The magnetic memory may include a plurality of magnetic storage cells, a plurality of bit lines corresponding to the plurality of magnetic storage cells, and a plurality of source lines corresponding to the plurality of magnetic storage cells. | 07-23-2009 |
| 20100067293 | Programmable and Redundant Circuitry Based On Magnetic Tunnel Junction (MTJ) - Techniques, apparatus and circuits based on magnetic or magnetoresistive tunnel junctions (MTJs). In one aspect, a programmable circuit device can include a magnetic tunnel junction (MTJ); a MTJ control circuit coupled to the MTJ to control the MTJ to cause a breakdown in the MTJ in programming the MTJ; and a sensing circuit coupled to the MTJ to sense a voltage under a breakdown condition of the MTJ. | 03-18-2010 |
K.t Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090039405 | ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD. | 02-12-2009 |
| 20090042378 | USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line. | 02-12-2009 |
| 20100264480 | USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains one or more charge storage nodes, a first poly gate, a pair of first bit lines, and a pair of second bit lines. The second bit line can be formed at a higher energy level, a higher concentration of dopants, or a combination thereof compared to an energy level and a concentration of dopants of the first bit line. | 10-21-2010 |
| 20110278660 | ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DISTURB - Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD. | 11-17-2011 |
Mark M. Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110304645 | TECHNIQUES FOR PROVIDING HOLISTIC VIEWS OF PERSONAL ENERGY CONSUMPTION - Techniques for providing holistic views of energy consumption. Energy consumption of one or more energy consuming devices corresponding to a user is monitored. The energy consumption for the one or more energy consuming devices is aggregated. A graphical representation of the energy consumption is provided to the user for the one or more energy consuming devices and aggregate energy consumption. The graphical representation comprises at least one visual metaphor for energy consumption. | 12-15-2011 |
Michael Alan Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100082176 | Peer-To-Peer Home Automation Management - A first home automation control device is configured to control a first electrical appliance and to communicate via a peer-to-peer network with a second home automation control device which is configured to control a second electrical appliance. When the first home automation control device discovers the presence of the second home automation control device, the first home automation control device negotiates with the second home automation control device to determine a goal. The first home automation control device and the second home automation control device then jointly execute a task to achieve the goal. The goal may be an energy savings goal. | 04-01-2010 |
| 20110137436 | INTELLIGENT GATEWAY FOR HETEROGENEOUS PEER-TO-PEER HOME AUTOMATION NETWORKS - A solution for home automation management includes, at a network device configured to support multiple home automation technologies, receiving a message from a first home automation control device (HACD) managed by the network device, towards a second HACD managed by the network device. The network device translates the message to a form recognizable by the second HACD, and then sends the translated message towards the second HACD in accordance with home automation technology supported by the second HACD. According to one aspect, the solution may be extended to a network of multiple network devices configured to support multiple home automation technologies. | 06-09-2011 |
Po-Chien Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100070751 | Preloader - This disclosure describes techniques and/or apparatuses for reducing the total time used to boot up a computer and load applications onto the computer. | 03-18-2010 |
| 20100254173 | DISTRIBUTED FLASH MEMORY STORAGE MANAGER SYSTEMS - A flash memory storage system may include several modules of flash memory storage manager circuitry, each having some associated flash memory. The modules may be interconnected via the flash memory storage manager circuitry of the modules. The system may be able to write data to and/or read data from the flash memory associated with various ones of the modules by routing the data through the flash memory storage circuitry of the modules. The system may also be able to relocate data for various reasons using such read and write operations. The flash memory storage circuitry of the modules keeps track of where data actually is in the flash memory. | 10-07-2010 |
| 20110068836 | SPREAD-SPECTRUM CLOCK ACQUISITION AND TRACKING - Apparatus having corresponding methods and computer-readable media comprise: a phase detector configured to generate an error signal representing a phase difference between a recovered spread-spectrum clock signal and a serial data stream that includes a spread-spectrum clock signal; and a phase selector configured to provide the recovered spread-spectrum clock signal based on an error signal from a current spread-spectrum cycle of the spread-spectrum clock signal and an error signal from a previous spread-spectrum cycle of the spread-spectrum clock signal. | 03-24-2011 |
| 20110119438 | FLASH MEMORY FILE SYSTEM - Apparatus having corresponding methods and computer-readable media comprise: a plurality of flash modules, wherein each of the flash modules comprises a cache memory; a flash memory; and a flash controller in communication with the cache memory and the flash memory; wherein the flash controller of a first one of the flash modules is configured to operate the cache memories together as a global cache; wherein the flash controller of a second one of the flash modules is configured to operate a second one of the flash modules as a directory controller for the flash memories. | 05-19-2011 |
Timothy Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090322370 | Method And Apparatus For Test And Characterization Of Semiconductor Components - A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system. | 12-31-2009 |
Tom Weiliang Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110207454 | AUTHENTICATING AND REGISTERING ROAMING MOBILE USERS - In an embodiment, a mobile device that is configured to receive calls on a first telephone network via a first telephone number is configured to receive calls on a second telephone network via a second telephone number. A subscriber interface module (SIM) is installed into the mobile device enabling the mobile device to communicate with the second telephone network. A username, password, and telephone number for the second network are obtained. The mobile device registers the username, password, telephone number for the first network and telephone number for the second network with the first telephone network. A telephone call is received from the first telephone network and a personal identification code is employed to verify the registration. | 08-25-2011 |
Tony Yuan-Kon Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080273548 | CONFIGURATION OF SERVICE GROUPS IN A CABLE NETWORK - A method and apparatus for configuring service groups in a cable network is provided. A method may comprise identifying a primary downstream channel in a cable network and identifying a plurality of fiber nodes fed by the primary downstream channel. For each fiber node identified, the method may comprise identifying a set of downstream channels communicating with the fiber node. If duplicate sets are identified, duplicate sets of downstream channels may be eliminated and a downstream service group may be associated with each of the remaining sets of downstream channels. In an example embodiment, at least one Media Access Control (MAC) domain is automatically selected to correspond to the identified service groups. | 11-06-2008 |
Tung Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100216506 | System and Methods for Supporting Multiple Communications Protocols on a Mobile Phone Device - A mobile phone device utilizing a first communications protocol and a second communications protocol, comprises: a first system having a general processor, a memory, a first communications system providing for the first communications protocol and utilizing a first communications protocol stack, and a first link; a second system having a dedicated communications accelerator providing for the second communications protocol and utilizing a second communications protocol stack, and a second link; wherein the first link and the second link are connected; and wherein the memory in the first system holds the first communications protocol stack and the second communications protocol stack. | 08-26-2010 |
| 20100216508 | Systems and Methods for Driving an External Display Device Using a Mobile Phone Device - A mobile phone device comprises the following: a processor; a first display controller for driving an internal display of the mobile phone device; and a second display controller for driving an external display, wherein the external display is connectable to the second display controller via a connector. | 08-26-2010 |
| 20100261466 | Systems and Methods for Operating a Virtual Whiteboard Using a Mobile Phone Device - A method for operating a virtual whiteboard using a mobile phone device, comprises the steps of: generating the virtual whiteboard, wherein the mobile phone device is coupled to the virtual whiteboard to input data to the virtual whiteboard; connecting the mobile phone device to an external display device; displaying the virtual whiteboard on the external display device; and operating the virtual whiteboard using the mobile phone device; wherein markings on the virtual whiteboard correspond to spatial movements of the mobile phone device. | 10-14-2010 |
Wanli Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080246516 | Phase Frequency Detectors Generating Minimum Pulse Widths - A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals. The one or more output signals have a minimum pulse width. The phase frequency detector has a temperature sensing circuit. The phase frequency detector adjusts the minimum pulse width of the one or more output signals using the temperature sensing circuit to compensate for variations in the temperature of the phase frequency detector. | 10-09-2008 |
| 20090267645 | PASSGATE STRUCTURES FOR USE IN LOW-VOLTAGE APPLICATIONS - Enhanced passgate structures for use in low-voltage systems are presented in which the influence of V | 10-29-2009 |
William I. Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110173179 | SEARCH ENGINE AND METHOD WITH IMPROVED RELEVANCY, SCOPE, AND TIMELINESS - A search engine and a method achieve timeliness of documents returned in a search result by a relevancy feedback mechanism driven by the frequency in which a URL is returned in recent searches. The relevancy feedback mechanism includes one or more random processes which determine whether or not a cached or indexed web page associated with a URL in the search result should be refreshed. In addition, the random processes also determine whether or not hyperlinks in the cached or indexed web page should be followed to access related web pages. Accesses of web pages resulting from the operations of the random processes are used to update any document index maintained by the search engine. Relevancy scoring functions implemented in look-up tables are also disclosed. A more accurate relevancy scoring function is achieved using a lexicon based on anchortexts of extracted hyperlinks of web documents. | 07-14-2011 |
| 20110173181 | SEARCH ENGINE AND METHOD WITH IMPROVED RELEVANCY, SCOPE, AND TIMELINESS - A search engine and a method achieve timeliness of documents returned in a search result by a relevancy feedback mechanism driven by the frequency in which a URL is returned in recent searches. The relevancy feedback mechanism includes one or more random processes which determine whether or not a cached or indexed web page associated with a URL in the search result should be refreshed. In addition, the random processes also determine whether or not hyperlinks in the cached or indexed web page should be followed to access related web pages. Accesses of web pages resulting from the operations of the random processes are used to update any document index maintained by the search engine. Relevancy scoring functions implemented in look-up tables are also disclosed. A more accurate relevancy scoring function is achieved using a lexicon based on anchortexts of extracted hyperlinks of web documents. | 07-14-2011 |
Yi Chang, Saratoga, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100158236 | System and Methods for Tracking Unresolved Customer Involvement with a Service Organization and Automatically Formulating a Dynamic Service Solution - A system for managing customer involvement with a contact center involves one or more monitoring applications executing on one or more computerized servers associated with the contact center, the applications monitoring communications between individual customers and the center; and a rules engine executing on the one or more computerized servers, the rules engine accessible to the monitoring application, the rules engine enabled to generate and implement business rules. Upon detection by one of the monitoring applications of an instance of unsuccessful or incomplete interaction between a customer and the contact center, session data determined during monitoring is used by the rules engine to determine contact center-initiated activity to be implemented to establish new communication with the customer to resolve issues related to the unsuccessful or incomplete interaction. | 06-24-2010 |
| 20100161540 | Method for Monitoring and Ranking Web Visitors and Soliciting Higher Ranked Visitors to Engage in Live Assistance - A ranking system ranks visitors to a Web site using one or more instances of machine-readable code executable from a digital medium accessible to a Web server. The code tracks visitor behavior while browsing the web site, and a visitor ranking module resident on the digital medium accepts information documented by the one or more instances of machine readable code and assigns rank values to one or more of the visitors. The ranking module ranks visitors at the Web-site based on logic and rules for interpreting visitor behavior and for applies a value to the visitor in real time based on that interpretation, and values applied at or above a preprogrammed level trigger solicitation of the visitor so ranked to engage in interaction including live assistance. | 06-24-2010 |