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| 20080236787 | METHOD TO COOL BAKE PLATES IN A TRACK LITHOGRAPHY TOOL - A method of reducing a temperature of a bake plate within a semiconductor processing tool includes (a) providing a substrate and (b) transferring the substrate to a position adjacent the bake plate. The bake plate is characterized by an initial bake plate temperature greater than a set point temperature. The method also includes (c) reducing the temperature of the bake plate by a first predetermined amount and (d) transferring the substrate from the position adjacent the bake plate to a position adjacent a chill plate. The chill plate is characterized by a chill plate temperature less than the set point temperature. The method further includes (e) transferring the substrate from the position adjacent the chill plate to the position adjacent the bake plate, (f) reducing the temperature of the bake plate by a second predetermined amount, (g) monitoring the temperature of the bake plate, and (h) repeating steps (d) through (g) until the bake plate temperature is within a predetermined tolerance of the set point temperature. | 10-02-2008 |
| 20100258049 | HVPE CHAMBER HARDWARE - Embodiments disclosed herein generally relate to an HVPE chamber. The chamber may have two separate precursor sources coupled thereto to permit two separate layers to be deposited. For example, a gallium source and a separate aluminum source may be coupled to the processing chamber to permit gallium nitride and aluminum nitride to be separately deposited onto a substrate in the same processing chamber. The nitrogen may be introduced to the processing chamber at a separate location from the gallium and the aluminum and at a lower temperature. The different temperatures causes the gases to mix together, react and deposit on the substrate with little or no deposition on the chamber walls. | 10-14-2010 |
| 20100258052 | HVPE PRECURSOR SOURCE HARDWARE - Embodiments disclosed herein generally relate to an HVPE chamber. The chamber may have two separate precursor sources coupled thereto to permit two separate layers to be deposited. For example, a gallium source and a separate aluminum source may be coupled to the processing chamber to permit gallium nitride and aluminum nitride to be separately deposited onto a substrate in the same processing chamber. The nitrogen may be introduced to the processing chamber at a separate location from the gallium and the aluminum and at a lower temperature. The different temperatures causes the gases to mix together, react and deposit on the substrate with little or no deposition on the chamber walls. | 10-14-2010 |
| 20100261340 | CLUSTER TOOL FOR LEDS - The present invention generally provides apparatus and methods for forming LED structures. One embodiment of the present invention provides a method for fabricating a compound nitride structure comprising forming a first layer comprising a first group-III element and nitrogen on substrates in a first processing chamber by a hydride vapor phase epitaxial (HVPE) process or a metal organic chemical vapor deposition (MOCVD) process, forming a second layer comprising a second group-III element and nitrogen over the first layer in a second processing chamber by a MOCVD process, and forming a third layer comprising a third group-III element and nitrogen over the second layer by a MOCVD process. | 10-14-2010 |
| 20110253044 | SHOWERHEAD ASSEMBLY WITH METROLOGY PORT PURGE - A method and apparatus that may be utilized for chemical vapor deposition and/or hydride vapor phase epitaxial (HVPE) deposition are provided. In one embodiment, the apparatus is a processing chamber that includes a showerhead with separate inlets and channels for delivering separate processing gases into a processing volume of the chamber without mixing the gases prior to entering the processing volume. In one embodiment, the showerhead includes metrology ports with purge gas assemblies configured and positioned to deliver a purge gas to prevent deposition thereon. In one embodiment, the metrology port is configured to receive a temperature measurement device, and the purge gas assembly is a concentric tube configuration configured to prevent deposition on components of the temperature measurement device. In one embodiment, the metrology port has a sensor window and is configured to receive an optical measurement device, and the purge gas assembly and sensor window are configured to prevent deposition on the sensor window. | 10-20-2011 |
| 20110256315 | SHOWERHEAD ASSEMBLY WITH GAS INJECTION DISTRIBUTION DEVICES - A method and apparatus that may be utilized for chemical vapor deposition and/or hydride vapor phase epitaxial (HVPE) deposition are provided. The apparatus includes a showerhead assembly with separate inlets and manifolds for delivering separate processing gases into a processing volume of the chamber without mixing the gases prior to entering the processing volume. The showerhead includes a plurality of gas distribution devices disposed within a plurality of gas inlets for injecting one of the processing gases into and distributing it across a manifold for uniform delivery into the processing volume of the chamber. Each of the gas distribution devices preferably has a nozzle configured to evenly distribute the processing gas flowing therethrough while minimizing recirculation of the processing gas within the manifold. As a result, improved deposition uniformity is achieved on a plurality of substrates positioned in the processing volume of the processing chamber. | 10-20-2011 |
| 20110256645 | MULTIPLE PRECURSOR SHOWERHEAD WITH BY-PASS PORTS - A method and apparatus that may be utilized for chemical vapor deposition and/or hydride vapor phase epitaxial (HVPE) deposition are provided. In one embodiment, the apparatus a processing chamber that includes a showerhead with separate inlets and channels for delivering separate processing gases into a processing volume of the chamber without mixing the gases prior to entering the processing volume. In one embodiment, the showerhead includes one or more cleaning gas conduits configured to deliver a cleaning gas directly into the processing volume of the chamber while by-passing the processing gas channels. In one embodiment, the showerhead includes a plurality of metrology ports configured to deliver a cleaning gas directly into the processing volume of the chamber while by-passing the processing gas channels. As a result, the processing chamber components can be cleaned more efficiently and effectively than by introducing cleaning gas into the chamber only through the processing gas channels. | 10-20-2011 |
| 20110256692 | MULTIPLE PRECURSOR CONCENTRIC DELIVERY SHOWERHEAD - A method and apparatus that may be utilized for chemical vapor deposition and/or hydride vapor phase epitaxial (HVPE) deposition are provided. In one embodiment, the apparatus provides a processing chamber that includes a showerhead with separate inlets and channels for delivering separate processing gases into a processing volume of the chamber without mixing the gases prior to entering the processing volume. In one embodiment, a plurality of concentric tube assemblies are disposed within the showerhead to separately deliver a first gas from a first gas channel and a second gas from a second gas channel into the processing volume of the chamber. In one embodiment, the showerhead further includes a heat exchanging channel through which the plurality of concentric tube assemblies is disposed. | 10-20-2011 |
| 20110308551 | METHOD AND APPARATUS FOR INDUCING TURBULENT FLOW OF A PROCESSING CHAMBER CLEANING GAS - Embodiments of the invention generally relate to apparatus and methods for cleaning chamber components using a cleaning plate. The cleaning plate is adapted to be positioned on a substrate support during a cleaning process, and includes a plurality of turbulence-inducing structures. The turbulence-inducing structures induce a turbulent flow of cleaning gas while the cleaning plate is rotated during a cleaning process. The cleaning plate increases the retention time of the cleaning gas near the showerhead during cleaning. Additionally, the cleaning plate reduces concentration gradients within the cleaning plate to provide a more effective clean. The method includes positioning a cleaning plate adjacent to a showerhead, and introducing cleaning gas to the space between the showerhead and the cleaning plate. A material deposited on the surface of the showerhead is then heated and vaporized in the presence of the cleaning gas, and then exhausted from the processing chamber. | 12-22-2011 |
| 20120012049 | HVPE CHAMBER - Embodiments disclosed herein generally relate to an HVPE chamber. The chamber may have one or more precursor sources coupled thereto. For example, a gallium source and a separate aluminum source may be coupled to the processing chamber to permit gallium nitride and aluminum nitride to be separately deposited onto a substrate in the same processing chamber. The nitrogen may be introduced to the processing chamber at a separate location from the precursors and at a lower temperature. The chamber has a truncated box shape formed by a curved cover which improves the flow of the nitrogen and precursor gases and the uniformity of the film deposition. | 01-19-2012 |
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| 20090150838 | METHOD OF PROGRESSIVELY PROTOTYPING AND VALIDATING A CUSTOMER'S ELECTRONIC SYSTEM DESIGN - A method for prototyping and validating a customer's electronic system design (ESD) with design data is proposed. The design data is partitioned into hierarchical design elements (HDEs) plus their respective test benches. The ESD couples with customer's customer peripheral devices CPDs via their peripheral interface terminals PITs thus forming interconnected hierarchical system elements (HSEs) interacting with one another according to a functional validation specification. The HSEs form numerous system hierarchy levels (SHLs). The method includes:
| 06-11-2009 |
| 20090150839 | INTEGRATED PROTOTYPING SYSTEM FOR VALIDATING AN ELECTRONIC SYSTEM DESIGN - An integrated prototyping system (IPS) is proposed for verifying and validating an electronic system design (ESD) with hierarchical design elements (HDEs). The IPS has: a) A reprogrammable logic device (RPLD) having an emulation timing base and an RPLD-interface for programming and simulating HDEs under validation while transacting exchanging vectors. The RPLD is also switchably coupled to numerous external peripheral electronic devices (PED), b) An EDA simulator for simulating then verifying selected HDEs while transacting exchanging vectors. The EDA simulator also has a simulator interface; and c) An IPS controller bridging the RPLD and the EDA simulator. The IPS controller has an IPS executive for progressively verifying and validating the ESD. The IPS executive further includes a co-emulation software for jointly and simultaneously running the RPLD and the EDA simulator with an event-based synchronization scheme for interchanging exchanging vectors on demand between the RPLD and the EDA simulator. | 06-11-2009 |
| 20100100860 | METHOD AND APPARATUS FOR DEBUGGING AN ELECTRONIC SYSTEM DESIGN (ESD) PROTOTYPE - Using a vector-based emulation technique, a hardware-based prototyping system reduces time-consuming recompilation and reduces the iteration time for a verification run. The vector-based emulation technique takes advantage of information derived from user-defined probe points, automatically generated probe points and low-latency snapshots. Using a bounded-cycle simulation technique, the hardware-based prototyping system can provide complete or partial simulation traces covering interested signals and can efficiently evaluates assertions. A user is therefore able to debug in a real system test and to identify causes of fault conditions interactively under a controlled vector debugging environment. | 04-22-2010 |
| 20100305933 | Method and Apparatus for Verifying Logic Circuits Using Vector Emulation with Vector Substitution - A method for verifying a logic circuit in a prototyping system includes (a) configuring programmable logic circuits of the prototyping system to implement the logic circuit and to implement probe circuits for accessing internal nodes of the logic circuit; (b) preparing emulation vectors for use in a vector emulation of the logic circuit in the prototyping system; (c) setting one or more vector substitution points; (d) preparing one or more packet vectors at each vector substitution point for replacing emulation vectors in the vector emulation; (e) performing the vector emulation using the emulation vectors until one of the vector substitution points is reached; and (f) substituting packet vectors for the corresponding emulation vectors at vector substitution point and continuing the vector emulation. | 12-02-2010 |
| 20110289469 | VIRTUAL INTERCONNECTION METHOD AND APPARATUS - A prototyping system includes (i) a vector processor having an interface for communicating with a host processor and a second interface (e.g., a vector processor bus) for dispatching vectors; (ii) a number of programmable logic circuits each coupled to the second interface to receive the dispatched vectors; and (iii) a compiler for (a) partitioning an electronic circuit into multiple partitions, assigning each partition to one of the programmable logic circuits, (b) providing multiple connections each provided for connecting signals among the partitions, (c) providing in each programmable logic circuit an interface circuit module that manages the connections among partitions using a virtual interconnection technique, and (d) assigning the physical interconnection resources, such as pins of the programmable logic circuits and physical wires on the boards. First and further assigns at least one virtual interconnection (secondary I/O) between partitions to realize the connections among partitions. The prototyping system is associated with a method for prototyping an electronic design, which includes (i) compiling an electronic design into (a) multiple partitions, each partition being compiled for implementation in a programmable logic circuit (e.g., a field programmable gate array integrated circuit), and (b) multiple connections that connect signals between the partition; and (ii) compiling into each programmable logic circuit an interface circuit module for managing the connections using a virtual interconnection technique. | 11-24-2011 |
| 20120005547 | SCALABLE SYSTEM DEBUGGER FOR PROTOTYPE DEBUGGING - A prototype debugging system controlled by a host processor over a host bus includes: (a) a vector processor interface bus; (b) one or more programmable logic circuits, at least one of which provided to implement: (i) a logic circuit under verification; (ii) one or more programmable embedded debug circuits each receiving a first group of selected signals from the logic circuit under verification and providing control signals for (1) selecting a portion of the first group of selected signals, or (2) affecting the values of a second group of selected signals in the logic circuit under verification based on a portion of the first group of selected signals satisfying a predetermined triggering condition, wherein the programmable embedded debug circuits each including a built-in memory for storing signal vectors, the programmable embedded debug circuits each being configured according to a trigger specification defining one or more trigger states and triggering conditions; and (iii) a local debugging controller that controls programmable embedded debug circuits and transfers signal vectors between the built-in memories of the programmable embedded debug circuits and the vector processor interface bus; and (c) a vector processor which controls transferring of signal vectors between the host processor and the vector processor interface bus. | 01-05-2012 |
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| 20080239548 | Multiple sector reassign on write error for disk drive - A disk drive includes a disk for storing information representing data, and a memory device. A method for writing includes locating a first data sector on a disk where a write operation fails, identifying the first data sector and a plurality of other data sectors near the first data sector as a grown defect, and storing the location of the first data sector and the plurality of other data sectors on a grown defect list. The memory device includes a list of grown defects that identifies a plurality of data sectors stored along a track between the first servo wedge and the second servo wedge on a selected track as data sectors which may not be written to. | 10-02-2008 |
| 20090034109 | DISK DRIVE APPARATUS AND MEDIA DEFECT DETECTION METHOD - According to one embodiment, a disk drive apparatus includes a defect table formed using more than one defect detection standard. Methods and devices are described using different defect detection standards to detect and map defects of different sizes and in specific regions that can affect drive operation. Also, methods and devices are described that provide fast and efficient defect scanning in selected regions due to utilization of error correction systems. Methods are shown where during defect detection a read/write gate assertion is triggered using a servo gate pulse. | 02-05-2009 |
| 20090034110 | DISK DRIVE APPARATUS AND MULTI-TASKING METHOD - A disk drive apparatus is shown that provides multi-tasking of firmware and hardware separately. A shared data structure is shown that permits queuing of multiple task requests and storing of multiple task results for later use, decreasing a need for wait time between components such as disk drive firmware and hardware. Further efficiencies are provided, including power saving modes when higher power disk drive components are not in use. | 02-05-2009 |
| 20110304935 | FLOATING GUARD BAND FOR SHINGLE MAGNETIC RECORDING - A hard disk drive that includes a disk with data written onto a plurality of tracks, a spindle motor that rotates the disk, and a head that is coupled to the disk. The disk drive also includes a circuit that writes data onto a first writable shingle band of tracks if the first writable shingle band is adjacent to a guard band of tracks. The first writable shingle band includes a number of tracks that is a function of a head width. The guard band of tracks is capable of becoming a writable shingle band. Changing the designation of a shingle band between guard and writable creates floating guard bands. The creation of floating guard bands allows for the writing of a single band without having to move and restore adjacent tracks until reaching a fixed guard band as required in the prior art. | 12-15-2011 |
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| 20080247081 | Flex cable assembly for vibration reduction in HDD applications - A hard disk drive flex cable assembly conveys data between a connector to a host system and a head stack assembly. It comprises a flex cable which in part has a first end for coupling to the connector, and a second end for coupling to the head stack assembly; and a stiffener coupled to the second end. The stiffener comprises an end formed to approximate a J-shape. A filling material is applied to the concave surface of the J-shape, whereby a dynamic response frequency of the flex cable assembly is moved away from a dynamic response frequency of the head stack assembly upon which the flex cable assembly is coupled. | 10-09-2008 |
| 20080247094 | Flex cable assembly for robust right angle interconnect - A hard disk drive flex cable assembly, for conveying data between a connector to a host system and a head stack assembly, comprises a flex cable, which in part has a first end for coupling to the connector, and a second end for coupling to the head stack assembly; and a stiffener coupled to the second end, wherein the stiffener supports at least one termination pad of the second end on three sides of the termination pad. | 10-09-2008 |
| 20080253028 | SYSTEM AND APPARATUS FOR VIBRATION DAMPING OF INTEGRATED LEAD SUSPENSIONS IN HIGH DENSITY MAGNETIC STORAGE DEVICES - An integrated lead suspension (ILS) has a constrained layer damper (CLD) that attenuates vibration of the ILS. The CLD may be applied over an already assembled ILS such that the CLD is applied to the cover layer, to the base layer, or to both. Alternatively, the ILS may be encapsulated via a deposition process such that a damping layer is sandwiched between the conductor layer and the cover layer of the ILS, between the conductor layer and the dielectric layer of the ILS, or both. | 10-16-2008 |
| 20090080113 | Vision guided system and method for micro-scale flex cable/integrated lead suspension solder pad positioning in HDD assembling process - An apparatus for positioning a component relative to an associated component. The apparatus includes a component receiver and onto which the component is disposed. The apparatus also includes an associated component receiver and onto which the associated component is disposed. The component receiver orients the component into a position for retaining the component to the associated component. The apparatus further includes a retention device driver for inserting a retention device, the retention device retaining the component to the associated component in the position. The apparatus also includes an optical position verifier for verifying the position of the component and the associated component. | 03-26-2009 |
| 20110026165 | SYSTEM AND APPARATUS FOR VIBRATION DAMPING OF INTEGRATED LEAD SUSPENSIONS IN HIGH DENSITY MAGNETIC STORAGE DEVICES - An integrated lead suspension (ILS) has a constrained layer damper (CLD) that attenuates vibration of the ILS. The CLD may be applied over an already assembled ILS such that the CLD is applied to the cover layer, to the base layer, or to both. Alternatively, the ILS may be encapsulated via a deposition process such that a damping layer is sandwiched between the conductor layer and the cover layer of the ILS, between the conductor layer and the dielectric layer of the ILS, or both. | 02-03-2011 |
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| 20090015791 | SYSTEM AND METHOD FOR GENERATING CORRESPONDENCE MAPPINGS USING INFRARED PATTERNS - A method performed by a display system is provided. The method includes projecting a first infrared pattern from a first projection plane of a first projector into a scene, capturing the first infrared pattern from the scene in a capture plane of at least one image capture device, and determining a first correspondence mapping between the first projector and the image capture device from at least the first infrared pattern in the first projection plane and the first infrared pattern in the capture plane. | 01-15-2009 |
| 20090027504 | System and method for calibrating a camera - A method of calibrating a camera includes capturing a set of dark images at each of a plurality of different exposure settings, thereby generating a plurality of sets of dark images. Each set of dark images is averaged, thereby generating a fixed pattern noise image corresponding to each one of the exposure settings. The method includes determining fixed pattern noise for at least one pixel of the camera based on an exposure setting of the camera and at least one of the fixed pattern noise images. | 01-29-2009 |
| 20090027523 | System and method for determining a gamma curve of a display device - A method of determining a gamma curve of a display device includes identifying a region of interest of a display surface of the display device. A centroid of the region of interest is calculated. A plurality of input levels is applied to the display device to generate a corresponding plurality of displayed images on the display surface. At least one image of each of the displayed images is captured with a camera. A gamma curve of the display device is calculated based on the captured images and the centroid. | 01-29-2009 |
| 20090037945 | MULTIMEDIA PRESENTATION APPARATUS, METHOD OF SELECTING MULTIMEDIA CONTENT, AND COMPUTER PROGRAM PRODUCT - Provided is a multimedia presentation apparatus comprising:
| 02-05-2009 |
| 20090037946 | Dynamically displaying content to an audience - A method of dynamically displaying content to an audience is disclosed. The method includes displaying content to the audience wherein at least a portion of the audience is proximate a display means, capturing a plurality of responses from the audience, aggregating the plurality of responses and dynamically updating the displayed content based on the aggregated plurality of responses. | 02-05-2009 |
| 20110292219 | APPARATUS AND METHODS FOR IMAGING SYSTEM CALIBRATION - A reference set of image features is determined from an electronic data file specifying a reference image in a reference coordinate space. Rendering information describing a physical rendering of the reference image is ascertained. Calibration-enabling data is derived from the reference set of the image features and the ascertained rendering information. The calibration-enabling data is provided to calibrate an imaging system. The calibration-enabling data may be stored. The imaging system may capture an image of the physical rendering of the reference image in relation to a capture coordinate space. An extracted set of image features may be extracted from the captured image. Respective ones of the image features in the reference and extracted sets may be matched. The imaging system may be calibrated based on matched ones of the image features and the rendering information. | 12-01-2011 |
| 20110309999 | MULTI-PROJECTOR SYSTEM AND METHOD - A method for automatic delivery of consistent imagery in a multi-projector system includes the steps of dividing the projectors into a plurality of sub-groups of projectors, each projector oriented to project a sub-frame to a sub-group display location, and adjusting the output of each projector in each sub-group to provide selected target display characteristics across all sub-groups. | 12-22-2011 |
| 20120014594 | METHOD FOR TONE MAPPING AN IMAGE - A method for tone mapping a digital image comprised of a plurality of high bit depth intensity values in linear space is disclosed. First, a plurality of liner intensity values are mapped from the linear space to a non-linear space ( | 01-19-2012 |
| 20120019670 | MULTI-PROJECTOR SYSTEM AND METHOD - A method for reducing view-dependent artifacts in a multi-projector system includes the steps of measuring, from multiple viewpoints, projection characteristics of an image projected by a multi-projector system, estimating view-dependent projection parameters that can reduce view-dependent artifacts, and computing rendering parameters for each projector so as to reduce the view-dependent artifacts. | 01-26-2012 |
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| 20090016440 | POSITION CODING FOR CONTEXT-BASED ADAPTIVE VARIABLE LENGTH CODING - Particular embodiments include a method, an apparatus, and logic embodied in tangible computer-readable medium that when executed carries out a method of encoding an ordered sequence of quantized transform coefficients of a block of image data. One embodiment is a context adaptive variable length coding method that includes position coding the positions of zero-valued and non-zero valued coefficients by either a mixed method that encodes either the run length of zeroes preceding a non-zero coefficient or the run length of nonzero-valued coefficients preceding a zero-valued coefficients. Another includes position coding that uses a variable length code for two parameters respectively indicating the number of zero-valued coefficient positions and nonzero-valued coefficient positions still to be coded. | 01-15-2009 |
| 20090086815 | CONTEXT ADAPTIVE POSITION AND AMPLITUDE CODING OF COEFFICIENTS FOR VIDEO COMPRESSION - A coding method, apparatus, and medium with software encoded thereon to implement a coding method. The coding method includes encoding the position of non-zero-valued coefficients in an ordered series of quantized transform coefficients of a block of image data, including encoding events using variable length coding using a plurality of variable length code mappings that each maps events to codewords, the position encoding including switching between the code mappings based on the context. The coding method further includes encoding amplitudes of the non-zero-valued coefficients using variable dimensional amplitude coding in the reverse order of the original ordering of the series. | 04-02-2009 |
| 20090087109 | REDUCED CODE TABLE SIZE IN JOINT AMPLITUDE AND POSITION CODING OF COEFFICIENTS FOR VIDEO COMPRESSION - A coding method, apparatus, and medium with software encoded thereon to implement a coding method. The coding method includes jointly encoding joint events that each are defined by a cluster of consecutive non-zero-valued coefficients, each joint event defined by three parameters: the number of zero-valued coefficients preceding the cluster, the number of non-zero-valued coefficients in the cluster, and an indication of which trailing coefficients up to a maximum number of M trailing coefficients have amplitude greater than 1, with the coding using a 3-dimensional joint VLC table. The method further includes encoding the amplitude of the non-zero-valued trailing coefficients that have amplitude greater than 1 encoding the amplitude of any remaining non-zero-valued coefficients in the clusters that have more than M non-zero-valued coefficients. | 04-02-2009 |
| 20090087113 | VARIABLE LENGTH CODING OF COEFFICIENT CLUSTERS FOR IMAGE AND VIDEO COMPRESSION - A coding method, apparatus, and medium with software encoded thereon to implement a coding method. The coding method includes encoding cluster of consecutive non-zero-valued coefficients, the encoding of a cluster including jointly encoding joint events that each are defined by at least two parameters: the number of zero-valued coefficients preceding the cluster, and the number of non-zero-valued coefficients in the cluster. The encoding of the cluster also includes encoding a parameter indicative of the number of amplitude-1 trailing non-zero-valued coefficients in the cluster, in one version with the parameter indicative of the number of trailing amplitude-1 coefficients part of the joint events such that the coding is according to a 3-dimensional joint variable length coding table. The method further includes encoding the amplitudes of the non-zero-valued coefficients that are not encoded by the joint encoding, e.g., encoding the amplitudes of the other than the trailing amplitude-1 coefficients. | 04-02-2009 |
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| 20080246015 | METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT - Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described. | 10-09-2008 |
| 20090017593 | METHOD FOR SHALLOW TRENCH ISOLATION - Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described. | 01-15-2009 |
| 20100173452 | METHOD TO FORM HIGH EFFICIENCY GST CELL USING A DOUBLE HEATER CUT - Embodiments of the present invention provide a method that includes providing wafer including multiple cells, each cell including at least one emitter. The method further includes performing a lithographic operation in a word line direction of the wafer across the cells to form pre-heater element arrangements, performing a lithographic operation in a bit line direction of the wafer across the pre-heater element arrangements to form a pre-heater element adjacent each emitter, and performing a lithographic operation in the word line direction across a portion of the pre-heater elements to form a heater element adjacent each emitter. Other embodiments are also described. | 07-08-2010 |
| 20110186960 | TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed. | 08-04-2011 |
| 20110186992 | RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES - Embodiments of the present disclosure provide a method, comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming one or more vias in the first surface of the semiconductor substrate, the one or more vias initially passing through only a portion of the semiconductor substrate without reaching the second surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, the redistribution layer being electrically coupled to the one or more vias, coupling one or more dies to the redistribution layer, forming a molding compound to encapsulate at least a portion of the one or more dies, and recessing the second surface of the semiconductor substrate to expose the one or more vias. Other embodiments may be described and/or claimed. | 08-04-2011 |
| 20110186998 | RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed. | 08-04-2011 |
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| 20110030209 | METHOD FOR FABRICATING THIN TOUCH SENSOR PANELS - A method for fabricating thin DITO or SITO touch sensor panels with a thickness less than a minimum thickness tolerance of existing manufacturing equipment. In one embodiment, a sandwich of two thin glass sheets is formed such that the combined thickness of the glass sheets does not drop below the minimum thickness tolerance of existing manufacturing equipment when thin film process is performed on the surfaces of the sandwich during fabrication. The sandwich may eventually be separated to form two thin SITO/DITO panels. In another embodiment, the fabrication process involves laminating two patterned thick substrates, each having at least the minimum thickness tolerance of existing manufacturing equipment. One or both of the sides of the laminated substrates are then thinned so that when the substrates are separated, each is a thin DITO/SITO panel having a thickness less than the minimum thickness tolerance of existing manufacturing equipment. | 02-10-2011 |
| 20110267283 | Kickback Voltage Equalization - Scanning gate lines in a gate driver system of a touch screen is provided. The gate driver system can include gate lines connected to display pixel transistors, a display driver that can generate first and second gate clock signals including first and second voltage transitions, respectively, and a gate drivers that can receive the first and second gate clock signals via gate clock lines and that can apply gate line signals, based on the gate clock signals, to the gate lines. A first voltage change generated in a common electrode line of the touch screen by the first voltage transition can be reduced by a second voltage change generated in the common electrode by the second voltage transition. | 11-03-2011 |
| 20110285640 | ELECTRIC FIELD SHIELDING FOR IN-CELL TOUCH TYPE THIN-FILM-TRANSISTOR LIQUID CRYSTAL DISPLAYS - Displays such as liquid crystal displays may be used in electronic devices. During operation of a display, electrostatic charges on the surface of the display may give rise to electric fields. One or more electric field shielding layers may be provided in the display to prevent the electric fields from disrupting operation of the liquid crystals material in the display. The shielding layers may be formed at a location in the stack of layers that make up the display that is above the liquid crystal material of the display. Touch sensors and thin film transistors may be located below the shielding layer. | 11-24-2011 |
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| 20100080275 | TRAINING OF THE NON-UPDATED DECISION FEEDBACK EQUALIZER FOR A 8-VSB RECEIVER - A method for training of a non-updated decision feedback equalizer is provided. The method comprising the steps of: providing a sequence of frames adapted to be received by a receiver; provide a sequence of synchronization frames interposed between a predetermined number of frames; and using at least part of the sequence of synchronization frames to train a decision feedback equalizer (DFE), thereby speeding up system convergence or making system convergence possible. | 04-01-2010 |
| 20100080276 | METHOD FOR NON-PILOT TONE DATA-AIDED CARRIER FREQUENCY TRACKING - A method comprising the steps of providing a slicer for slicing real values of an equalizer output; and cross correlating an equalizer input with an output of the slicer is provided. | 04-01-2010 |
| 20100080277 | USING CONJUGATE GRADIENT METHOD TO CALCULATE FILTER COEFFICIENT FOR TIME DOMAIN EQUALIZER - A method used in a time domain equalizer is provided. A method comprising the steps of: providing a time domain equalizer comprising a feed forward equalizer and a feedback equalizer; and using a conjugate gradient iteration in order to calculate a set of coefficients of the time domain equalizer. | 04-01-2010 |
| 20100080278 | FILTER STRUCTURE IMPLEMENTATION RELATING TO A LINEAR SYSTEM SOLUTION - A method used in a time domain equalizer is provided. A method comprising the steps of: providing a time domain equalizer comprising a feed forward equalizer and a feedback equalizer; and using a filter circuit or structured implementation to incorporate conjugate gradient iteration in order to calculate a set of coefficients of the time domain equalizer. Whereby matrix times vector operations is converted into filtering using the filter circuit. | 04-01-2010 |
| 20100080280 | DECISION FEEDBACK EQUALIZER WITH PARTIAL FEEDBACK EQUALIZER IN A VARIABLE SIDEBAND COMMUNICATIONS SYSTEM - In a receiver of a multi-leveled variable sideband communications system, a method is provided that comprises the steps of: dividing the receiver into a real portion and a complex portion; and providing a decision feedback equalizer (DFE) processing data substantially in the real portion. | 04-01-2010 |
| 20100080281 | METHOD TO CALCULATE THE REAL DECISION FEEDBACK EQUALIZER COEFFICIENTS - A method used in a time domain equalizer is provided. The method comprising the steps of: providing a time domain equalizer comprising; and extracting a real part of an input or a derivative of the input to the time domain equalizer and using the only real part of the input in the time domain equalizer to derive an output of the time domain equalizer. | 04-01-2010 |
| 20100082720 | CURVE-FITTING METHOD TO CALCULATE COARSE FREQUENCY OFFSET - A method comprising the steps of: providing a known sequence comprising a plurality of data points; and curve-fitting the plurality of data points to calculate coarse frequency offset. | 04-01-2010 |
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| 20080202425 | TEMPERATURE CONTROLLED LID ASSEMBLY FOR TUNGSTEN NITRIDE DEPOSITION - Embodiments of the invention provide apparatuses for vapor depositing tungsten-containing materials, such as metallic tungsten and tungsten nitride. In one embodiment, a processing chamber is provided which includes a lid assembly containing a lid plate, a showerhead, a mixing cavity, a distribution cavity, and a resistive heating element contained within the lid plate. In one example, the resistive heating element is configured to provide the lid plate at a temperature within a range from about 120° C. to about 180° C., preferably, from about 140° C. to about 160° C., more preferably, from about 145° C. to about 155° C. The mixing cavity may be in fluid communication with a tungsten precursor source containing tungsten hexafluoride and a nitrogen precursor source containing ammonia. In some embodiments, a single processing chamber may be used to deposit metallic tungsten and tungsten nitride materials by CVD processes. | 08-28-2008 |
| 20080206987 | PROCESS FOR TUNGSTEN NITRIDE DEPOSITION BY A TEMPERATURE CONTROLLED LID ASSEMBLY - Embodiments of the invention provide processes for vapor depositing tungsten-containing materials, such as metallic tungsten and tungsten nitride. In one embodiment, a method for forming a tungsten-containing material is provided which includes positioning a substrate within a processing chamber containing a lid plate, heating the lid plate to a temperature within a range from about 120° C. to about 180° C., exposing the substrate to a reducing gas during a pre-nucleation soak process, and depositing a first tungsten nucleation layer on the substrate during a first atomic layer deposition process within the processing chamber. The method further provides depositing a tungsten nitride layer on the first tungsten nucleation layer during a vapor deposition process, depositing a second tungsten nucleation layer on the tungsten nitride layer during a second atomic layer deposition process within the processing chamber, and exposing the substrate to another reducing gas during a post-nucleation soak process. | 08-28-2008 |
| 20080268645 | METHOD FOR FRONT END OF LINE FABRICATION - In one embodiment, a method for removing native oxides from a substrate surface is provided which includes supporting a substrate containing silicon oxide within a processing chamber, generating a plasma of reactive species from a gas mixture within the processing chamber, cooling the substrate to a first temperature of less than about 65° C. within the processing chamber, and directing the reactive species to the cooled substrate to react with the silicon oxide thereon while forming a film on the substrate. The film usually contains ammonium hexafluorosilicate. The method further provides positioning the substrate in close proximity to a gas distribution plate, and heating the substrate to a second temperature of about 100° C. or greater within the processing chamber to sublimate or remove the film. The gas mixture may contain ammonia, nitrogen trifluoride, and a carrier gas. | 10-30-2008 |
| 20090111280 | METHOD FOR REMOVING OXIDES - A method for removing native oxides from a substrate surface is provided. In one embodiment, the method comprises positioning a substrate having an oxide layer into a processing chamber, generating a plasma of a reactive species from a gas mixture within the processing chamber, exposing the substrate to the reactive species while forming a volatile film on the substrate and maintaining the substrate at a temperature below 65° C., heating the substrate to a temperature of at least about 75° C. to vaporize the volatile film and remove the oxide layer, and depositing a first layer on the substrate after heating the substrate. | 04-30-2009 |
| 20090139854 | CONTROL OF ARBITRARY SCAN PATH OF A ROTATING MAGNETRON - A control system and method for controlling two motors determining the azimuthal and circumferential position of a magnetron rotating about the central axis of the sputter chamber in back of its target sputtering and capable of a nearly arbitrary scan path, e.g., with a planetary gear mechanism. A system controller periodically sends commands to the motion controller which closely controls the motors. Each command includes a command ticket, which may be one of several values. The motion controller accepts only commands having a command ticket of a different value from the immediately preceding command. One command selects a scan profile stored in the motion controller, which calculates motor signals from the selected profile. Another command instructs a dynamic homing command which interrogates sensors of the position of two rotating arms to determine if the arms in the expected positions. If not, the arms are rehomed. | 06-04-2009 |
| 20090218324 | DIRECT REAL-TIME MONITORING AND FEEDBACK CONTROL OF RF PLASMA OUTPUT FOR WAFER PROCESSING - A method and apparatus for controlling power output of a capacitatively-coupled plasma are provided. A detector is disposed on the power delivery conduit carrying power to one electrode to detect fluctuations in power output to the electrode. The detector is coupled to a signal generator, which converts the RF input signal to a constant control signal. A controller adjusts power input to the RF generator by comparing the control signal to a reference. | 09-03-2009 |
| 20100096085 | PLASMA REACTOR WITH A CEILING ELECTRODE SUPPLY CONDUIT HAVING A SUCCESSION OF VOLTAGE DROP ELEMENTS - A bridge assembly includes an electrically insulating hollow tube or bridge having a pair of ends, the bridge being supported at one of the ends over the cylindrical side wall and being supported at the other of the ends over the electrode. The bridge assembly further includes a set of conductive rings surrounding the hollow tube and spaced from one another along the length of the bridge, and plural electrically resistive elements. Each of the resistive elements has a pair of flexible connectors, respective ones the resistive elements connected at their flexible connectors between respective pairs of the rings to form a series resistor assembly. | 04-22-2010 |
| 20110223755 | METHOD FOR REMOVING OXIDES - A method for removing native oxides from a substrate surface is provided. In one embodiment, the method comprises positioning a substrate having an oxide layer into a processing chamber, generating a plasma of a reactive species from a gas mixture within the processing chamber, exposing the substrate to the reactive species while forming a volatile film on the substrate and maintaining the substrate at a temperature below 65° C., heating the substrate to a temperature of at least about 75° C. to vaporize the volatile film and remove the oxide layer, and depositing a first layer on the substrate after heating the substrate. | 09-15-2011 |
