| Patent application number | Description | Published |
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| 20090279561 | Backplane Interface Adapter - A backplane interface adapter for a network switch. The backplane interface adapter includes at least one receiver that receives input cells carrying packets of data; at least one cell generator that generates encoded cells which include the packets of data from the input cells; and at least one transmitter that transmits the generated cells to a switching fabric. The cell includes a destination slot identifier that identifies a slot of the switching fabric towards which the respective input cell is being sent. The generated cells include in-band control information. | 11-12-2009 |
| 20090290499 | Backplane Interface Adapter with Error Control and Redundant Fabric - A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric. | 11-26-2009 |
| 20100034215 | Backplane Interface Adapter with Error Control - A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric. | 02-11-2010 |
| 20110268108 | Backplane Interface Adapter with Error Control and Redundant Fabric - A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric. | 11-03-2011 |
| 20120026868 | Backplane Interface Adapter - A backplane interface adapter for a network switch. The backplane interface adapter includes at least one receiver that receives input cells carrying packets of data; at least one cell generator that generates encoded cells which include the packets of data from the input cells; and at least one transmitter that transmits the generated cells to a switching fabric. The cell includes a destination slot identifier that identifies a slot of the switching fabric towards which the respective input cell is being sent. The generated cells include in-band control information. | 02-02-2012 |
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| 20080298739 | System and method for fabricating an optical isolator - There is provided a system and method for fabricating an optical isolator. More specifically, there is provided a fiber optical isolator comprising a first isolator stage comprising a Faraday rotator configured to adjust the polarity of a light beam, and a heat sink coupled to the Faraday rotator and configured to dissipate heat generated in the Faraday rotator by the light beam. | 12-04-2008 |
| 20100040095 | Systems and methods for controlling a pulsed laser by combining laser signals - An ultra-short pulsed laser system comprises an optical combiner, optical amplifier, optical pulse compressor, and optical separator. The optical combiner is configured to combine a primary optical pulse with a secondary optical signal to generate a combined optical signal. The primary optical pulse and the secondary optical signal have a distinguishable characteristic. The optical amplifier is configured to optically amplify the combined optical signal. The optical pulse compressor is configured to compress at least the primary optical pulse contained within the optically amplified combined optical signal and output a compressed combined optical signal. The optical separator is configured to separate the compressed combined optical signal into an output primary optical pulse and an output secondary optical signal according to the distinguishable characteristic. | 02-18-2010 |
| 20100149641 | Compact Monolithic Dispersion Compensator - An optical signal control system is constructed from a portion of a material and allows for controlled amount of negative dispersion to be generated across a broadband input signal. The block may be made of a single portion of the material and have surfaces with reflective, transmissive, and/or diffractive optical characteristics. By adjusting the physical dimensions of the block substrate and the line pitch of a diffraction grating etched into a surface of the block, the magnitude of the dispersion can be varied. Laser systems that utilize the optical signal control system may have reduced size and weight as compared to existing compressors and be more robust against misalignment. | 06-17-2010 |
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| 20090031091 | CONTINUOUS TIMING CALIBRATED MEMORY INTERFACE - A system that adjusts the timing of write operations at a memory controller is described. This system operates by observing timing drift for read data at the memory controller, and then adjusting the timing of write operations at the memory controller based on the observed timing drift for the read data. | 01-29-2009 |
| 20090128207 | Clock Circuitry for Generating Multiple Clocks with Time-Multiplexed Duty Cycle Adjustment - Clocking circuitry includes a first clock generator to generate a first clock signal and having a first duty cycle correction input, and a second clock generator to generate a second clock signal and having a second duty cycle correction input. Some embodiments have more than two clock generators. A multiplexer selects between the clock signals from the clock generators. The multiplexer has a first input coupled to the first clock signal and has a second input coupled to the second clock signal, and has a clock output coupled to a clock input of a duty cycle circuit. The duty cycle circuit receives the selected clock signal from the multiplexer and generates a duty cycle correction signal. | 05-21-2009 |
| 20100058100 | DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS - A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function. | 03-04-2010 |
| 20100235554 | RECONFIGURABLE POINT-TO-POINT MEMORY INTERFACE - Embodiments of an apparatus are described. An interface circuit in this apparatus receives or transmits digital signals on a bus and is configured to alternatively operate as either a data-bus interface circuit or a control-bus interface circuit in dependence upon a mode setting stored in a register. For example, the interface circuit may be pre-configured to interpret a line of an external bus as either a data line or a control line in accordance with the stored mode setting. Moreover, the stored mode setting may be dynamically configured (e.g., reprogrammed) during operation of the interface circuit so that subsequent digital signals are subsequently handled in accordance with a new mode setting. | 09-16-2010 |
| 20100239057 | DRIFT CANCELLATION TECHNIQUE FOR USE IN CLOCK-FORWARDING ARCHITECTURES - A circuit includes a frequency synthesizer, N phase mixers coupled to the frequency synthesizer, a plurality of receivers, and a calibration circuit. The frequency synthesizer is to receive a reference clock signal and is to output a primary clock signal. A respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase. A respective receiver in the plurality of receivers is coupled to two of the N phase mixers, and at a respective time is to receive data in accordance with the respective secondary clock signal from one of the two phase mixers coupled to the respective receiver. The calibration circuit is to calibrate a secondary clock signal output by a respective phase mixer in the N phase mixers by adjusting the phase of the secondary clock signal of the respective phase mixer. | 09-23-2010 |
| 20100281289 | Bidirectional Memory Interface with Glitch Tolerant Bit Slice Circuits - A bit slice circuit having transmit and receive modes of operation is described. The bit slice circuit comprises: first transmit circuitry and first receive circuitry operating in a first clock domain, wherein the first circuitry receives a first clock signal; second transmit circuitry and second receive circuitry operating in a second clock domain, wherein the second circuitry receives a second clock signal; transmit transition circuitry and receive transition circuitry, the transmit transition circuitry coupling the first transmit circuitry to the second transmit circuitry, the receive transition circuitry coupling the first receive circuitry to the second receive circuitry, wherein the transition circuitry receives the first and second clock signals; and a single phase mixer that generates the second clock signal, wherein the second clock signal has a first phase in the transmit mode of operation and second phase in the receive mode of operation. | 11-04-2010 |
| 20110249774 | Partial Response Equalizer and Related Method - A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs. | 10-13-2011 |
| 20120014427 | Methods and Apparatus for Determining a Phase Error in Signals - An integrated circuit includes samplers, a phase error determination circuit, and periodic signal generators. The samplers generate respective sampled signals by sampling respective input signals in response to respective periodic signals. The input signals have a common phase error. The phase error determination circuit receives the sampled signals from the samplers. The phase error determination circuit generates a representation of the common phase error of the input signals in response to sampled signals received in a set-up mode in which the samplers sample respective input signals having a common bit pattern. The periodic signal generators generate the periodic signals differing in phase from one another by defined phase differences in the set-up mode and subject the periodic signals to a common phase shift in a normal mode in response to the representation of the common phase error. The common phase shift matches the common phase error of the input signals. | 01-19-2012 |
| 20120099678 | Drift Cancellation Technique for Use in Clock-Forwarding Architectures - A circuit includes a frequency synthesizer, N phase mixers coupled to the frequency synthesizer, a plurality of receivers, and a calibration circuit. The frequency synthesizer is to receive a reference clock signal and is to output a primary clock signal. A respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase. A respective receiver in the plurality of receivers is coupled to two of the N phase mixers, and at a respective time is to receive data in accordance with the respective secondary clock signal from one of the two phase mixers coupled to the respective receiver. The calibration circuit is to calibrate a secondary clock signal output by a respective phase mixer in the N phase mixers by adjusting the phase of the secondary clock signal of the respective phase mixer. | 04-26-2012 |
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| 20080265301 | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications - A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer. | 10-30-2008 |
| 20090111265 | SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK - Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device. | 04-30-2009 |
| 20100099249 | SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK - Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device. | 04-22-2010 |
| 20100230743 | SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS - A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer. | 09-16-2010 |
