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Chang Jun
Chang Jun Choi, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100039146 | High-Speed Multiplexer and Semiconductor Device Including the Same - High speed multiplexers include a first N-to-1 selection circuit, where N is an integer greater than one, a second N-to-1 selection circuit and an output driver. The first N-to-1 selection circuit is configured to route a true or complementary version of a selected first input signal (from amongst N input signals) to an output thereof in response to a first multi-bit selection signal, where N is an integer greater than one. The second N-to-1 selection circuit is configured to route a true or complementary version of the selected first input signal to an output thereof in response to a second multi-bit selection signal. The output driver includes a pull-up circuit, which is responsive to a signal generated at the output of the first N-to-1 selection circuit, and a pull-down circuit, which is responsive to a signal generated at the output of the second N-to-1 selection circuit. | 02-18-2010 |
Chang Jun Park, Kyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090189267 | SEMICONDUCTOR CHIP WITH CHIP SELECTION STRUCTURE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip with a chip selection structure suitable for a stacked semiconductor chip includes a semiconductor chip body and a chip selection structure. The chip selection structure includes a chip selection pad disposed over the semiconductor chip body, a main through electrode electrically connected to the chip selection pad, and a sub through electrode interposed between the main through electrode and the chip selection pad. A plurality of the semiconductor chips, each having the same chip selection structure, can be stacked by offsetting the stacked semiconductor chips. | 07-30-2009 |
Chang Jun Yoon, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100276667 | NONVOLATILE MEMORY ELECTRONIC DEVICE INCLUDING NANOWIRE CHANNEL AND NANOPARTICLE-FLOATING GATE NODES AND A METHOD FOR FABRICATING THE SAME - A nonvolatile memory electronic device including nanowire channel and nanoparticle-floating gate nodes, in which the nonvolatile memory electronic device, which comprises a semiconductor nanowire used as a charge transport channel and nanoparticles used as a charge trapping layer, is configured by allowing the nanoparticles to be adsorbed on a tunneling layer deposited on a surface of the semiconductor nanowire, whereby charge carriers moving through the nanowire are tunneled to the nanoparticles by a voltage applied to a gate, and then, the charge carriers are tunneled from the nanoparticles to the nanowire by the change of the voltage that has been applied to the gate, whereby the nonvolatile memory electronic device can be operated at a low voltage and increase the operation speed thereof. | 11-04-2010 |
Chang Jun Yu, Pasadena, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090012091 | Oximide derivatives and their therapeutical application - The present invention relates to a compound represented as the following Formula (I) and a pharmaceutical composition thereof | 01-08-2009 |