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| 20080265929 | Process Monitor for Monitoring and Compensating Circuit Performance - A method and system for monitoring and compensating the performance of an operational circuit is provided. The system includes one or more integrated circuit chips and a controller. Each integrated circuit chip includes one or more operational circuits, each operational circuit having at least one controllable circuit parameter. Each integrated circuit chip also includes a process monitor module at least partially constructed thereon. The controller is coupled to each process monitor module and to each operational circuit. The controller includes logic for evaluating the performance of an operational circuit based on data obtained from process monitor module and operational circuit related data stored in a memory. Based on the evaluation, the controller determines whether any deviations from desired or optimal performance of the circuit exist. If deviations exist, the controller generates a control signal to initiate adjustments to the operational circuit to compensate for the deviations. | 10-30-2008 |
| 20080284919 | Fully integrated tuner architecture - An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. | 11-20-2008 |
| 20090085597 | Process Monitor for Monitoring an Integrated Circuit Chip - A system or apparatus for monitoring an Integrated Circuit (IC) chip includes: a sense circuit at least partially constructed on the IC chip and configured to produce one or more sense signals each indicative of a corresponding process-dependent circuit parameter of the IC chip; and a digitizer module configured to produce, responsive to the one or more sense signals, one or more digitized signals each representative of a corresponding one of the sense signals. A controller is configured to determine a value of one or more of the process-dependent circuit parameters based on one or more of the digitized signals. | 04-02-2009 |
| 20100245012 | Integrated Spiral Inductor - An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors with shields to increase circuit Q. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading. | 09-30-2010 |
| 20110067083 | Fully Integrated Tuner Architecture - An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. | 03-17-2011 |
| 20110284840 | Process Monitor for Monitoring an Integrated Circuit Chip - A system or apparatus for monitoring an Integrated Circuit (IC) chip includes: a sense circuit at least partially constructed on the IC chip and configured to produce one or more sense signals each indicative of a corresponding process-dependent circuit parameter of the IC chip; and a digitizer module configured to produce, responsive to the one or more sense signals, one or more digitized signals each representative of a corresponding one of the sense signals. A controller is configured to determine a value of one or more of the process-dependent circuit parameters based on one or more of the digitized signals. | 11-24-2011 |
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| 20080227409 | WIRELESS RECEIVER WITH NOTCH FILTER TO REDUCE EFFECTS OF TRANSMIT SIGNAL LEAKAGE - This disclosure describes techniques for reducing adverse effects of TX signal leakage in a full-duplex, wireless communication device. The techniques make use of a notch filter to reject TX signal leakage in a signal processed in the RX path of the wireless communication device. The notch filter may be constructed as a complex notch filter using passive resistor and capacitor components to produce a notch frequency that attenuates TX signal leakage components in a desired signal. The notch filter may be applied to a down-converted, baseband signal produced by a passive mixer. | 09-18-2008 |
| 20090174481 | MULTI-LINEARITY MODE LNA HAVING A DEBOOST CURRENT PATH - A modified derivative superposition (MDS) low noise amplifier (LNA) includes a main current path and a cancel current path. Third-order distortion in the cancel path is used to cancel third-order distortion in the main path. In one novel aspect, there is a separate source degeneration inductor for each of the two current paths, thereby facilitating tuning of one current path without affecting the other current path. In a second novel aspect, a deboost current path is provided that does not pass through the LNA load. The deboost current allows negative feedback to be increased without generating headroom problems. In a third novel aspect, the cancel current path and/or deboost current path is programmably disabled to reduce power consumption and improve noise figure in operational modes that do not require high linearity. | 07-09-2009 |
| 20090258624 | METHOD AND APPARATUS FOR PROCESSING A COMMUNICATION SIGNAL IN A RECEIVER - A receiver includes a jammer detector configured to detect the presence or the absence of jamming in a communication signal within a gain state. The receiver further includes an amplifier configured to amplify the communication signal in a high linearity receiving mode or a low linearity receiving mode, wherein the high linearity receiving mode corresponds with a lower gain for the gain state in the amplifier relative to that of the low linearity receiving mode. In addition, the receiver includes a processing unit coupled to the jammer detector, the processing unit being configured to control the amplifier to amplify the communication signal in either the high linearity receiving mode or the low linearity receiving mode, based on the output of the jammer detector detecting the presence or the absence of jamming in the communication signal. A method is also provided for processing a communication signal in a receiver. | 10-15-2009 |
| 20110037518 | AMPLIFIERS WITH IMPROVED LINEARITY AND NOISE PERFORMANCE - Amplifiers with improved linearity and noise performance are described. In an exemplary design, an apparatus includes first through sixth transistors. The first transistor receives an input signal and provides an amplified signal. The second transistor receives the amplified signal and provides signal drive for an output signal. The third transistor receives the input signal and provides an intermediate signal. The fourth transistor provides bias for the third transistor in a high linearity mode. The fifth transistor receives the intermediate signal and provides signal drive for the output signal in a low linearity mode. The third and fourth transistors form a deboost path that is enabled in the high linearity mode to improve linearity. The third and fifth transistors form a cascode path that is enabled in the low linearity mode to improve gain and noise performance. The sixth transistor generates distortion component used to cancel distortion component from the first transistor. | 02-17-2011 |
| 20110110463 | RECEIVER WITH BALANCED I/Q TRANSFORMER - A receiver with a balanced I/Q transformer is described. In an exemplary design, the receiver includes an LNA that amplifies a received RF signal and provides a single-ended RF signal to the balanced I/Q transformer. The balanced I/Q transformer includes at least one primary coil and first and second secondary coils. The first secondary coil is magnetically coupled to the at least one primary coil and provides a first differential RF signal to a first mixer. The second secondary coil is magnetically coupled to the at least one primary coil and provides a second differential RF signal to a second mixer. The first and second mixers downconvert the first and second differential RF signals with I and Q LO signals, respectively, and provide differential I and Q downconverted signals. The primary and secondary coils may be fabricated on two conductive layers of an integrated circuit. | 05-12-2011 |
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| 20090031044 | High-Speed MAC Address Search Engine - Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a frame forwarding device such as a switch. The switch includes two MAC address tables including a primary MAC address table and secondary MAC address table both for storing and searching MAC addresses. The primary table stores records that contain compressed values of MAC addresses. The records are contained in storage locations that are referenced using the compressed value of the MAC address as a search index. In order to account for searching collisions that may result from different MAC addresses compressing to the same value, each record in the primary address table is linked to a chain of records in the secondary table. The records in the secondary table store the full value of the MAC address. Each chain of records in the secondary address table contains MAC addresses the present invention. | 01-29-2009 |
| 20090086733 | Compact Packet Switching Node Storage Architecture Employing Double Data Rate Synchronous Dynamic RAM - A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks. The method relates to a packet data transfer discipline addressing random memory access latencies incurred in employing DDR SDRAM, using predictive bank switching to hide random access latencies, packet length dependent variable memory write burst lengths to minimize bank switching, and performing memory read and write operations during corresponding read and write windows. Advantages are derived from the a space-efficient two-chip/single-die switching node architecture implemented with a reduced amount of dual mode logic, and also from DDR SDRAM bandwidth utilization efficiencies. | 04-02-2009 |
