Patent application number | Description | Published |
20090111541 | PORTABLE TERMINAL - A portable terminal is provided that has a terminal body, a receiver located in the terminal body, the receiver being oriented in a first direction, and a ground unit located in the terminal body. The ground unit includes a first ground portion connected to the receiver, and a second ground portion connected to the first ground portion at a position on the first ground portion at a distance from the receiver. The second ground portion is configured to emit electromagnetic waves in a second direction away from the first direction. | 04-30-2009 |
20090124294 | PORTABLE TERMINAL - Disclosed is a portable terminal capable of enhancing compatibility with a hearing aid. The portable terminal comprises a terminal case having a sound hole thereon; a receiver installed inside the sound hole; and a reflection unit disposed between the terminal case and the receiver, for reflecting an electromagnetic wave radiated from an interior or a surface of the terminal case so as to minimize leakage of the electromagnetic wave to outside of the terminal case. | 05-14-2009 |
20090124306 | PORTABLE TERMINAL - A portable terminal is capable of enhancing a Hearing Aid Compatibility (HAC) rating by having an arrangement to shift a peak region of an electromagnetic field occurring at the time of a wireless communication in a call mode, to a position far from a measuring region. | 05-14-2009 |
20110012795 | PORTABLE TERMINAL - A portable terminal comprises: a terminal body having a receiver for sound output; a first antenna disposed in the terminal body, and operating at a first band; a second antenna disposed at a position different from the first antenna, and operating at a second band, wherein the second antenna comprises: a first conductor having a physical condition to be operable at the second band; and a second conductor having a physical condition to resonate an electromagnetic wave of the first band so as to reduce a field strength of the first band near the to receiver. | 01-20-2011 |
Patent application number | Description | Published |
20080316840 | Input/output line sense amplifier and semiconductor memory device using the same - An input/output (I/o) line sense amplifier includes a buffer unit, a sense amplifier, and a precharge unit. The buffer unit is driven by a first level voltage to buffer a strobe signal, and the sense amplifier is driven by a second level voltage to amplify a signal of an I/O line in response to an output signal of the buffer unit. The precharge unit is driven by the first level voltage to precharge an output signal of the sense amplifier in response to the output signal of the buffer unit. | 12-25-2008 |
20090109776 | Sense amplifier driving circult and semiconductor device having the same - The semiconductor memory device blocks a power supply voltage, which is supplied to the sense amplifier, in a write operation, or pull-down drives first and second local I/O lines LIO and LIOB lest they reach the level of ground voltage Vss. Driving time of a write driver of the semiconductor memory device is reduced, and current consumption is reduced. A sense amplifier driving circuit of a semiconductor memory device includes a transfer unit for transferring first and second control signals in response to an enable signal which is activated in a write operation, and a power supply unit for supplying first and second power supply voltages to a sense amplifier in response to the first and second control signals. | 04-30-2009 |
20100020626 | Input/output line sense amplifier and semiconductor memory device using the same - An input/output (I/o) line sense amplifier includes a buffer unit, a sense amplifier, and a precharge unit. The buffer unit is driven by a first level voltage to buffer a strobe signal, and the sense amplifier is driven by a second level voltage to amplify a signal of an I/O line in response to an output signal of the buffer unit. The precharge unit is driven by the first level voltage to precharge an output signal of the sense amplifier in response to the output signal of the buffer unit. | 01-28-2010 |
Patent application number | Description | Published |
20140117354 | SEMICONDUCTOR PACKAGE - A semiconductor package including a first semiconductor package including a first terminal and a second terminal provided on a surface different from a surface on which the first terminal is formed, and a second semiconductor package including a third terminal connected to the first terminal, wherein the surface on which the first terminal is formed faces a surface on which the third terminal is formed. | 05-01-2014 |
20140117430 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first substrate, a plurality of memory chips horizontally disposed on the first substrate, and having one surfaces which face the first substrate, other surfaces which face away from the one surfaces, and first bumps formed on the other surfaces, a second substrate disposed on the plurality of memory chips and electrically connected, a sub-substrate horizontally disposed on the first substrate together with the plurality of memory chips and electrically connecting the first substrate and the second substrate, and a driving chip having second bumps on one surface thereof and mounted to the second substrate such that the second bumps are electrically connected with the second substrate. | 05-01-2014 |
20140124921 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate; a driving chip having first bumps on a first surface and bump pads on a second surface facing away from the first surface, and mounted to the substrate by the medium of the first bumps; a support member disposed on the substrate substantially horizontally with respect to the driving chip; and a plurality of memory chips substantially horizontally disposed on the driving chip and the support member such that one corner portions of the memory chips are positioned on the driving chip while being centered about the driving chip, wherein the respective memory chips have second bumps which are electrically connected with the respective bump pads of the driving chip, on one surfaces of the one corner portions of the memory chips which face the driving chip. | 05-08-2014 |
20140167280 | SEMICONDUCTOR DEVICE - A semiconductor device including a chip stack structure having a plurality of semiconductor chips, the semiconductor chips being stacked such that they are electrically connected using through-electrodes, and a support frame attached to a side surface of the chip stack structure. | 06-19-2014 |
20140241079 | CHIP DIE AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A chip die including a first input/output (I/O) pad configured to transmit/receive an I/O signal of a memory cell array included in the chip die; a second I/O pad configured to, if a stacked chip die exists on the chip die, transmit/receive a via I/O signal of the stacked chip die, and configured to, if the stacked chip die does not exist on the chip die, transmit/receive a differential I/O signal of the chip die; and an I/O driver configured to receive an operation mode signal including information as to whether the stacked chip die exists on the chip die in such a manner that the second I/O pad is configured to transmit/receive the via I/O signal or the differential I/O signal. | 08-28-2014 |
20140284795 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Various embodiments are directed to a semiconductor package and a method for manufacturing the same. A semiconductor package includes the following: a substrate having a plurality of connection pads; a semiconductor chip provided with a plurality of bonding pads on a first surface thereof and attached onto the substrate in a face-down position so that the bonding pads are positioned right above the corresponding connection pads; and thermoplastic conductive members introduced between the substrate and the semiconductor chip such that the bonding pad and the corresponding connection pad may be electrically connected. | 09-25-2014 |
20140285253 | STACK PACKAGE - A stack package may include a plurality of chips stacked with a plurality of layers; and a chip selection controller configured to provide a reference and chip selection control signal to the plurality of chips. Each chip may comprise: a reference signal controller configured to transmit the reference signal through a first line interconnecting the plurality of chips; a chip selection delay unit configured to control a delay timing point of the chip selection control signal to transmit the control result to each node of a second line interconnecting the plurality of chips; a delay-time-difference sensing unit configured to calculate a delay time difference between a signal applied to each node of the first and second line to generate chip selection information corresponding to the calculated delay time difference; and a memory unit configured to store the chip selection information. | 09-25-2014 |
20140328104 | SEMICONDUCTOR DEVICE - A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and second internal input/output circuit units for exchanging signals; first external input/output circuit unit for exchanging signals through first external input/output pads formed according to an external interface standard of a first memory over the second surface; and second external input/output circuit unit for exchanging signals through second external input/output pads formed according to an external interface standard of a second memory over the second surface, wherein semiconductor device operates in one of a first mode in which the first internal input/output circuit unit and the first external input/output circuit unit are enabled and a second mode in which the first and second internal input/output circuit units and the second external input/output circuit unit are enabled. | 11-06-2014 |
20150084689 | SEMICONDUCTOR CHIP INCLUDING A SPARE BUMP AND STACKED PACKAGE HAVING THE SAME - A stacked package including: a semiconductor substrate, a circuit layer formed over the semiconductor substrate, a bump formed over the circuit layer, a spare bump formed correspondingly to the bump and over the circuit layer, and configured for replacing the bump with the spare bump, a through electrode configuring to pass through the semiconductor substrate on a same line as the bump and electrically coupled the bump or the spare bump in response to a selection signal, and a spare through electrode configured to pass through the semiconductor substrate on a same line as the spare bump and electrically coupled with the bump or the spare bump in response to a selection signal. When a bump has failed, a vertical input/output line of the semiconductor chips is established by a spare bump corresponding to the failed bump through the selective signal routing. | 03-26-2015 |