Patent application number | Description | Published |
20090020805 | NON-VOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced. | 01-22-2009 |
20090027967 | NON-VOLATILE MEMORY DEVICE PROGRAMMING SELECTION TRANSISTOR AND METHOD OF PROGRAMMING THE SAME - A memory system includes a flash memory device and a memory controller for controlling the flash memory device. The flash memory device includes a cell string and a selection transistor connected in series to the cell string. The cell string includes multiple series-connected memory cells. The selection transistor has the same structure as a memory cell of the series-connected memory cells, and is programmed through channel hot electron injection. | 01-29-2009 |
20090040836 | NAND flash memory device and method of programming the same - Provided are a NAND flash memory device and a method of programming the same. The NAND flash memory device may include a cell array including a plurality of pages; a page buffer storing program data of the pages; a data storage circuit providing program verification data to the page buffer; and a control unit. The control unit may program the pages and verify the pages using the program verification data following the programming of at least two of the pages. | 02-12-2009 |
20090097546 | SYSTEM AND METHOD FOR ENHANCED VIDEO COMMUNICATION USING REAL-TIME SCENE-CHANGE DETECTION FOR CONTROL OF MOVING-PICTURE ENCODING DATA RATE - Disclosed is a method for detecting a scene change in real time in order to control a moving-picture encoding data rate, the method including: dividing a current frame into a plurality of regions, and calculating a dissimilarity metric (DM) of each divided region; determining if the dissimilarity metric of each divided region is beyond a preset reference value; calculating the number of regions, the dissimilarity metric of which is beyond the preset value, in the current frame; and determining that a scene change occurs in the current frame, when the number of regions, the dissimilarity metric of which is beyond the reference preset value, is equal to or greater than a preset threshold value. | 04-16-2009 |
20090230451 | Semiconductor device capable of suppressing short channel effect and method of fabricating the same - A semiconductor device includes a semiconductor substrate including at least one memory channel region and at least one memory source/drain region, the memory channel region and the memory source/drain region being arranged alternately, and at least one word line on the memory channel region, wherein the memory source/drain region has a higher net impurity concentration than the memory channel region. | 09-17-2009 |
20100027617 | METHOD AND APPARATUS FOR COMPRESSING A REFERENCE FRAME IN ENCODING/DECODING MOVING IMAGES - Provided is a method of compressing a reference frame in encoding or decoding moving images. A reference frame to be compressed is divided into basic processing blocks. The basic processing blocks are divided into sub-blocks. A maximum value and a minimum value of pixels within each sub-block are calculated. A necessary bit length needed for compression of each sub-block is obtained based on a difference between the maximum value and the minimum value. An average bit length of the sub-blocks within the basic processing block is calculated based on the calculated necessary bit lengths of the sub-blocks. Bits are variably allocated to each sub-block by adjusting the necessary bit length of each sub-block so that the average bit length of the sub-blocks within a corresponding basic processing block is less than or equal to a preset required bit length. Each sub-block is compressed to the allocated bits. | 02-04-2010 |
20100046625 | APPARATUS AND METHOD FOR VIDEO ENCODING AND DECODING - A method and apparatus for encoding an image based on a video sensor structure are provided. The method includes acquiring an image to be encoded; separating the acquired image into respective color components; creating a predicted image for each of the color components, and creating a residual image between the predicted image and the acquired image; and performing transform encoding on each of the color components individually by applying the residual image to a transformation formula. | 02-25-2010 |
20100317157 | CELL ARRAY OF SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FORMING THE SAME - A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region. | 12-16-2010 |
20110266608 | NONVOLATILE MEMORY DEVICES HAVING GATE STRUCTURES DOPED BY NITROGEN - Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein. | 11-03-2011 |
20110274180 | METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING LAYERED CODED VIDEO - Transmitting and receiving a layered coded video, in which a picture of a base layer and a picture of at least one enhancement layer are separately encoded, the encoded pictures of the base layer and the encoded pictures of the at least one enhancement layer are arranged on a slice basis, the arranged pictures are packetized by adding a header to the rearranged pictures, and the packets are transmitted as a bit stream. | 11-10-2011 |
20120007168 | SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING SHORT CHANNEL EFFECT - A semiconductor device includes a semiconductor substrate including at least one memory channel region and at least one memory source/drain region, the memory channel region and the memory source/drain region being arranged alternately, and at least one word line on the memory channel region, wherein the memory source/drain region has a higher net impurity concentration than the memory channel region. | 01-12-2012 |
20120037975 | SEMICONDUCTOR DEVICES - A semiconductor device has an isolation layer pattern, a plurality of gate structures, and a first insulation layer pattern. The isolation layer pattern is formed on a substrate and has a recess thereon. The gate structures are spaced apart from each other on the substrate and the isolation layer pattern. The first insulation layer pattern is formed on the substrate and covers the gate structures and an inner wall of the recess. The first insulation layer pattern has a first air gap therein. | 02-16-2012 |
20120093425 | ENTROPY ENCODING/DECODING METHOD AND APPARATUS FOR HIERARCHICAL IMAGE PROCESSING AND SYMBOL ENCODING/DECODING APPARATUS FOR THE SAME - Entropy decoding, after encoding, includes performing symbol decoding on a bitstream of a received residual picture in units of two, three, or four symbols according to a context model which is set in the two, three, or four symbol units, and ordering the decoded coefficients of the residual picture in their original order in the frequency domain. Symbol and level decoding may be performed together. A unique symbol value may be used. | 04-19-2012 |
20120132982 | Non-Volatile Memory Devices - A non-volatile memory device includes gate structures, an insulation layer pattern, and an isolation structure. Multiple gate structures being spaced apart from each other in a first direction are formed on a substrate. Ones of the gate structures extend in a second direction that is substantially perpendicular to the first direction. The substrate includes active regions and field regions alternately and repeatedly formed in the second direction. The insulation layer pattern is formed between the gate structures and has a second air gap therein. Each of the isolation structures extending in the first direction and having a first air gap between the gate structures, the insulation layer pattern, and the isolation structure is formed on the substrate in each field region. | 05-31-2012 |
20120139027 | VERTICAL STRUCTURE NON-VOLATILE MEMORY DEVICES INCLUDING IMPURITY PROVIDING LAYER - A vertical structure non-volatile memory device includes a channel region that vertically extends on a substrate. A memory cell string vertically extends on the substrate along a first wall of the channel regions, and includes at least one selection transistor and at least one memory cell. An impurity providing layer is disposed on a second wall of the channel region and includes impurities. | 06-07-2012 |
20120146118 | NON-VOLATILE MEMORY DEVICE WITH HIGH SPEED OPERATION AND LOWER POWER CONSUMPTION - A semiconductor memory device has a memory cell region and a peripheral region. The device includes low voltage transistors at the peripheral region having gate insulation films with different thicknesses. For example, a gate insulation film of a low voltage transistor used in an input/output circuit of the memory device may be thinner than the gate insulation film of a low voltage transistor used in a core circuit for the memory device. Since low voltage transistors used at an input/output circuit are formed to be different from low voltage transistors used at a core circuit or a high voltage pump circuit, high speed operation and low power consumption characteristics of a non-volatile memory device may be. | 06-14-2012 |
20120288007 | METHOD AND APPARATUS FOR ENCODING VIDEO USING VARIABLE PARTITIONS FOR PREDICTIVE ENCODING, AND METHOD AND APPARATUS FOR DECODING VIDEO USING VARIABLE PARTITIONS FOR PREDICTIVE ENCODING - A video encoding method and apparatus and a video decoding method and apparatus are provided. The video encoding method includes: prediction encoding in units of a coding unit as a data unit for encoding a picture, by using partitions determined based on a first partition mode and a partition level, so as to select a partition for outputting an encoding result from among the determined partitions; and encoding and outputting partition information representing a first partition mode and a partition level of the selected partition. The first partition mode represents a shape and directionality of a partition as a data unit for performing the prediction encoding on the coding unit, and the partition level represents a degree to which the coding unit is split into partitions for detailed motion prediction. | 11-15-2012 |
20130092996 | NAND FLASH MEMORY DEVICES - NAND flash memory device includes a common bit line, a first cell string including a first string selecting transistor having a first gate length, a second string selecting transistor having a second gate length, first cell transistors each having a third gate length and a first ground selecting transistor having a fourth gate length, a second cell string including a third string selecting transistor having the first gate length, a fourth string selecting transistor having the second gate length, second cell transistors each having the third gate length and a second ground selecting transistor having the fourth gate length and a common source line commonly connected to end portions of the first and second ground selecting transistors included in the first and second cell strings. At least one of the first gate length and the second gate length is smaller than the fourth gate length. | 04-18-2013 |
20130142447 | METHOD AND APPARATUS FOR ENCODING AND DECODING IMAGE - Methods and apparatuses for encoding and decoding an image in which a block is searched for based on a representative value, rather than being searched for on a pixel-by-pixel basis, thereby search speed may be increased and computational complexity of a search operation may be reduced. | 06-06-2013 |
20130258771 | METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE - In method of programming a nonvolatile memory device including first and second cell strings that are coupled to one bitline, a first channel of the first cell string and a second channel of the second cell string are precharged by applying a first voltage to the bitline, one cell string is selected from the first and second cell strings, and a memory cell included in the selected cell string is programmed by applying a second voltage greater than a ground voltage and less than the first voltage to the bitline. | 10-03-2013 |
20140106518 | NONVOLATILE MEMORY DEVICES - A nonvolatile memory device includes a string selection transistor, a plurality of memory cell transistors, and a ground selection transistor electrically connected in series to the string selection transistor and to the pluralities of memory cell transistors. First impurity layers are formed at boundaries of the channels and the source/drain regions of the memory cell transistors. The first impurity layers are doped with opposite conductivity type impurities relative to the source/drain regions of the memory cell transistors. Second impurity layers are formed at boundaries between a channel and a drain region of the string selection transistor and between a channel and a source region of the ground selection transistor. The second impurity layers are doped with the same conductivity type impurities as the first impurity layers and have a higher impurity concentration than the first impurity layers. | 04-17-2014 |
20140160854 | NON-VOLATILE MEMORY DEVICES AND METHODS OF OPERATING THE SAME - A non-volatile memory device includes a semiconductor substrate and a tunnel insulating layer and a gate electrode. A multiple tunnel insulation layer with a plurality of layers, a charge storage insulation layer, and a multiple blocking insulation layer with layers are sequentially stacked between the gate electrode and the tunnel insulating layer. A first diffusion region and a second diffusion region in the semiconductor substrate are adjacent to opposite respective sides of the gate electrode. When a voltage is applied to the gate electrode and the semiconductor substrate to form a voltage level difference therebetween, a minimum field in the tunnel insulation layer is stronger than in the blocking insulation layer. A minimum field at a blocking insulation layer can be stronger than at a tunnel insulation layer, and the migration probability of charges through the tunnel insulation layer can be higher than through the blocking insulation layer. | 06-12-2014 |
20140203346 | VERTICAL TYPE SEMICONDUCTOR DEVICES INCLUDING A METAL GATE AND METHODS OF FORMING THE SAME - Vertical type semiconductor devices including a metal gate and methods of forming the vertical type semiconductor devices are provided. The vertical type semiconductor devices may include a channel pattern. The vertical type semiconductor devices may also include first and second gate patterns sequentially stacked on a sidewall of the channel pattern. The first and second gate pattern may include first and second metal elements, respectively and the second gate pattern may have a resistance lower than a resistance of the first gate pattern. | 07-24-2014 |
20140264548 | Semiconductor Devices and Methods of Manufacturing the Same - A memory device may include a plurality of semiconductor patterns on a substrate including a plurality of first impurity regions doped at a first impurity concentration, a plurality of second impurity regions at portions of the substrate contacting the plurality of semiconductor patterns and doped at a second impurity concentration, a plurality of channel patterns on the plurality of semiconductor patterns, a plurality of gate structures, a plurality of third impurity regions at portions of the substrate adjacent to end portions of the plurality of gate structures, and a plurality of fourth impurity regions at portions of the substrate between the second and third impurity regions and between adjacent second impurity regions. The plurality of fourth impurity regions may be doped at a third impurity concentration which may be lower than the first and second impurity concentrations. | 09-18-2014 |
20140264549 | VERTICAL MEMORY DEVICES WITH VERTICAL ISOLATION STRUCTURES AND METHODS OF FABRICATING THE SAME - A vertical memory device includes a substrate, a column of vertical channels on the substrate and spaced apart along a direction parallel to the substrate, respective charge storage structures on sidewalls of respective ones of the vertical channels and gate electrodes vertically spaced along the charge storage structures. The vertical memory device further includes an isolation pattern disposed adjacent the column of vertical channels and including vertical extension portions extending parallel to the vertical channels and connection portions extending between adjacent ones of the vertical extension portions. | 09-18-2014 |
20140269080 | NON-VOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME - A non-volatile memory device includes a memory cell array and a voltage generator. The memory cell array has a plurality of cell strings in which a plurality of memory cells are connected with each other in series between a string select transistor and a ground select transistor. The voltage generator generates a program voltage, a first pass voltage, and a second pass voltage. A first boost channel voltage applied when programming an outermost memory cell from among the memory cells of each of non-selected cell strings of the cell strings is lower than a second boost channel voltage applied when programming one of remaining memory cells except for the outermost memory cell. The non-volatile memory device prevents programming disturb caused by hot carrier injection. | 09-18-2014 |
20150060977 | SEMICONDUCTOR DEVICES WITH VERTICAL CHANNEL STRUCTURES - Semiconductor devices are provided. The semiconductor devices may include a substrate, a ground selection gate electrode, and a channel structure. The channel structure may extend the ground selection gate electrode in a first direction perpendicular to a top surface of the substrate, and include a channel layer, a channel contact layer, and a stepped portion. The channel contact layer may contact the substrate and include a first width in a second direction perpendicular to the first direction. The channel layer may contact the channel contact layer, include a bottom surface between a bottom surface of the ground selection gate electrode and the top surface of the substrate in the first direction, and include a second width in the second direction different from the first width. | 03-05-2015 |