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Chang-Hyun Lee
Chang-Hyun Lee, Kyungki-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090129165 | Nonvolatile Memory Devices and Methods of Operating Same to Inhibit Parasitic Charge Accumulation Therein - Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing a first plurality of nonvolatile memory cells in the first string and then selectively erasing a second plurality of nonvolatile memory cells in the first string, which may be interleaved with the first plurality of nonvolatile memory cells. This operation to selectively erase the first plurality of nonvolatile memory cells may include erasing the first plurality of nonvolatile memory cells while simultaneously biasing the second plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the second plurality of nonvolatile memory cells. The operation to selectively erase the second plurality of nonvolatile memory cells may include erasing the second plurality of nonvolatile memory cells while simultaneously biasing the first plurality of nonvolatile memory cells in a blocking condition that inhibits erasure of the first plurality of nonvolatile memory cells. | 05-21-2009 |
| 20110069543 | Methods of Operating Nonvolatile Memory Devices to Inhibit Parasitic Charge Accumulation Therein - Methods of operating a charge trap nonvolatile memory device include operations to erase a first string of nonvolatile memory cells by selectively erasing even-numbered nonvolatile memory cells in the first string and then selectively erasing the odd-numbered nonvolatile memory cells in the first string, which may be interleaved with the even-numbered nonvolatile memory cells. This operation to selectively erase the even-numbered nonvolatile memory cells may include erasing the even-numbered nonvolatile memory cells while simultaneously biasing the odd-numbered nonvolatile memory cells in a blocking condition that inhibits erasure of the odd-numbered nonvolatile memory cells. The operation to selectively erase the odd-numbered nonvolatile memory cells may include erasing the odd-numbered nonvolatile memory cells while simultaneously biasing the even-numbered nonvolatile memory cells in a blocking condition that inhibits erasure of the even-numbered nonvolatile memory cells. | 03-24-2011 |
Chang-Hyun Lee US
| Patent application number | Description | Published |
|---|---|---|
| 20110045647 | METHODS OF FORMING NON-VOLATILE MEMORY DEVICES - A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced. | 02-24-2011 |
Chang-Hyun Lee, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080240043 | METHOD FOR PERFORMING HANDOVER BY CONSIDERING QUALITY OF SERVICE IN BROADBAND MOBILE COMMUNICATION SYSTEM AND SYSTEM FOR PROVIDING THE SAME - A system and method for performing a handover of a mobile station (MS) by considering Quality of Service (QoS) in a broadband mobile communication system. The method can include the steps of: receiving information about one or more neighbor base stations and reception strengths for the neighbor base stations from a Serving Radio Access System (RAS) currently communicating with the MS; extracting a value of a specific field from the received information about the neighbor base stations; combining the extracted value of the specific field with the reception strengths to thereby obtain combined values, and selecting a maximum value among the combined values; and transmitting a handover (handoff) request message to a base station corresponding to the selected maximum value. The system includes an MS that analyzes information about neighbor stations received in a Mobile Neighbor Base-station Advertisement (MOB_NBR_ADV) message to select a target RAS. | 10-02-2008 |
| 20080259834 | CROSS-LAYER OPTIMIZATION METHOD FOR CONTROLLING BIT RATE OF VIDEO CODEC IN TRANSMISSION OF VIDEO DATA IN WIBRO SYSTEM - A cross-layer optimization method for controlling a bit rate of a video coder/decoder (codec) in video data transmission for wireless devices such as a wireless broadband (WiBro) system terminal that adapts to changing transmission/reception characteristics and usage. The method typically includes checking, by a sender, radio channel state information of a sender side and a receiver side; determining, by the sender, a transmission bit rate of a video codec by using the radio channel state information of the sender side; and adjusting, by the sender, the transmission bit rate of the video codec by using the radio channel state information of the receiver side when a communication network used by a receiver typically based on the type of a communication network being used by the sender. | 10-23-2008 |
| 20090022218 | METHOD FOR CONTROLLING MOVING PICTURE ENCODING USING CHANNEL INFORMATION OF WIRELESS NETWORKS - Disclosed is a method for controlling bit rates in consideration of wireless channel environment by an apparatus that transmits and receives moving picture encoding data via a wireless network. The apparatus for transmitting/receiving data through a wireless communication network connected to the apparatus including a channel state analyzing unit for analyzing a wireless channel environment, an encoding controller for generating control information containing information about a quantization parameter, skip or non-skip of frames indication, frame type indication, and use or non-use of an Error Resilient Tool (ERT) indication, in consideration of an analyzation result received from the channel state analyzing unit, a moving picture encoding unit for encoding incoming moving picture data, based on the control information received from the encoding controller; and a data transmitting/receiving unit for transferring the encoded moving picture data through the wireless channel to an exterior. | 01-22-2009 |
| 20090097405 | METHOD FOR SETTING OUTPUT BIT RATE FOR VIDEO DATA TRANSMISSION IN A WIBRO SYSTEM - A method for setting an output bit rate for video data transmission in a WiBro system in which an uplink state value for a predetermined unit time is calculated to determine an uplink network state of the predetermined unit time. An average of uplink state values for a predetermined number of unit times is calculated, and a video encoding bit rate is increased if the average of the uplink state values is larger than a predetermined first threshold. However, the video encoding bit rate is decreased if the average of the uplink state values is less than a predetermined second threshold. | 04-16-2009 |
| 20090153668 | SYSTEM AND METHOD FOR REAL-TIME VIDEO QUALITY ASSESSMENT BASED ON TRANSMISSION PROPERTIES - A system and method for video quality assessment includes utilizing codec auxiliary information related to the encoding and decoding process to enhance performance of picture quality assessment. In a video transmission system, video quality assessment can be accurately performed in real time with reduced computational load upon the client. In particular, the server performs first picture quality assessment and sends the assessment result to the client, and the client performs second picture quality assessment only when a transmission error occurs to reduce the computational load on the client. | 06-18-2009 |
| 20100232292 | METHOD FOR VARIABLY CONTROLLING BIT RATE OF VIDEO DATA THROUGH END-TO-END CHANNEL STATUS SENSING IN A WIBRO NETWORK - A method for variably controlling a bit rate of video data through end-to-end channel status sensing in a Wireless Broadband (WiBro) network is provided. The method includes classifying wireless channel statuses of a transmission side and a reception side into normal and abnormal statuses during video data transmission; variably controlling and determining an encoding bit rate of a transmission side's encoder according to the classification result; and comparing the determined encoding bit rate with a Down Link Modulation & Coding Selection Level (DL MCS Level) which is a parameter of the reception side, so as to vary a final encoding bit rate of the transmission side. | 09-16-2010 |
| 20110014544 | PROTON EXCHANGE POLYMER MEMBRANE USING SURFACE TREATMENT TECHNIQUE BASED ON DIRECT FLUORINATION, MEMBRANE-ELECTRODE ASSEMBLY, AND FUEL CELL COMPRISING THE SAME - A proton exchange polymer membrane whose surface is treated by direct fluorination using a fluorine gas, a membrane-electrode assembly, and a fuel cell comprising the same are provided. The proton exchange polymer membrane of the present invention exhibits improved proton conductivity, high dimensional stability, and decreased methanol permeability through introducing hydrophobic fluorine having high electronegativity to the surface of the polymer membrane. Therefore, the proton exchange polymer membrane with excellent electrochemical properties of the present invention can be preferably utilized as polymer electrolyte membrane for fuel cell, generating electric energy from chemical energy of fuels. | 01-20-2011 |
Chang-Hyun Lee, Suwon-Cityi KR
| Patent application number | Description | Published |
|---|---|---|
| 20100157668 | Memory device and method of operating and fabricating the same - A memory transistor including a substrate, a tunnel insulating pattern on the substrate, a charge storage pattern on the tunnel insulating pattern, a blocking insulating pattern on the charge storage pattern, and a gate electrode on the blocking insulating pattern, the blocking insulating pattern surrounding the gate electrode and methods of operating and fabricating the same. A nonvolatile memory may further include a plurality of memory transistors in series and a plurality of auxiliary structures between each of the plurality of unit transistors in series. Each of the plurality of auxiliary structures may be a dummy mask pattern or an assistant gate structure. | 06-24-2010 |
| 20100327371 | Memory device and method of fabricating the same - A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series. | 12-30-2010 |
Chang-Hyun Lee, Kyunggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080265307 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES - A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer. | 10-30-2008 |
| 20090294838 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICES - A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer. | 12-03-2009 |
Chang-Hyun Lee, Gyeongi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090212340 | FLASH MEMORY DEVICES - A gate electrode line which extends in a second direction crossing a first direction on a substrate including an active region which is defined by a device isolation layer and extends in the first direction and a charge trap layer disposed between the active region and the gate electrode line, wherein a bottom surface of the gate electrode line disposed on the device isolation layer is lower than a top surface of the charge trap layer disposed on the active region and higher than a top surface of the active region. | 08-27-2009 |
Chang-Hyun Lee, Suwon-City KR
| Patent application number | Description | Published |
|---|---|---|
| 20090046505 | FLASH MEMORY DEVICES AND OPERATING METHODS THAT CONCURRENTLY APPLY DIFFERENT PREDETERMINED BIAS VOLTAGES TO DUMMY FLASH MEMORY CELLS THAN TO REGULAR MEMORY CELLS DURING ERASE - Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than to the regular flash memory cells during an erase operation of the integrated circuit flash memory device. Related methods are also described. | 02-19-2009 |