| Patent application number | Description | Published |
|---|
| 20090302902 | POWER UP SIGNAL GENERATION CIRCUIT AND METHOD FOR GENERATING POWER UP SIGNAL - A power up signal generation circuit transits a power up signal at a predetermined target voltage level by providing a predetermined hysteresis characteristic to the target voltage level of a power supply voltage corresponding to the power up signal. The power up signal generation circuit includes a first voltage detection unit that detects a first target voltage level of a power supply voltage to output a detection signal. The circuit also includes a second voltage detection unit that detects a second target voltage level of the power supply voltage in response to a power up signal to output a control signal, wherein the second target voltage level is lower than the first target voltage level. A power up signal drive unit of the circuit activates the power up signal in response to the detection signal and drives the power up signal in response to the control signal. | 12-10-2009 |
| 20090303650 | MONITORING CIRCUIT FOR SEMICONDUCTOR DEVICE - Provided is a technology for monitoring the electrical resistance of an element such as a fuse whose resistance is changed due to the electrical stress among internal circuits included in a semiconductor device. The present invention provides a monitoring circuit to monitor the change in the device specification during the device is being programmed and after the device is programmed. The present invention enables the verification of an optimized condition to let the device have a certain electrical resistance, by comparing the load voltage and the fuse voltage with the reference voltage that can sense the range of resistance variation more precisely. Also, it can guarantee device reliability since it is still possible to sense electrical resistance after the electrical stress is being given. Also, the present invention can increase the utility of the fuse by possessing an output to monitor electrical resistance sensed inside of the semiconductor. | 12-10-2009 |
| 20100008001 | ELECTROSTATIC DISCHARGE PROTECTION OF SEMICONDUCTOR DEVICE - A semiconductor device includes a pads for receiving a reference voltage and input signals from an external device, a unit gain buffer for receiving the reference voltage as an input, input buffers for identifying a corresponding one of the input signals based on an internal reference voltage outputted from the unit gain buffer, external electrostatic discharge protectors connected to a transmission path of the reference voltage and transmission paths of input signals, and internal electrostatic discharge protectors connected to the transmission path of the reference voltage and the transmission paths of the input signals. | 01-14-2010 |
| 20100008162 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR GENERATING BIT LINE EQUALIZING SIGNAL - A bit line equalizing signal generator of a semiconductor memory device uses a supply voltage and a pumping voltage in stages during a period where a bit line equalizing signal is enabled, thereby enhancing an equalizing speed and an active speed while minimizing power consumption. The semiconductor memory device includes a bit line equalizing signal generating unit configured to drive an output terminal with the supply voltage during a first activation period at the beginning of the period where the bit line equalizing signal is enabled, and to drive the output terminal with the pumping voltage higher than the supply voltage during a second activation period following the first activation period, thereby outputting the bit line equalizing signal, and a bit line equalizing unit configured to equalize a bit line pair in response to the bit line equalizing signal. | 01-14-2010 |
| 20100110811 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first data input circuit configured to align data inputted to a first data pad in parallel for transferring the aligned data to a first global bus and for transferring the aligned data to a second global bus in a test mode; and a second data input circuit configured to align data inputted to a second data pad in parallel for transferring the aligned data to the second global bus and to not receive data in the test mode. | 05-06-2010 |
| 20100277999 | FUSE CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A fuse circuit includes a fuse unit configured to drive an output terminal via a current path including a fuse in response to a fuse enable signal; and a comparison unit configured to be activated in response to an activation signal for comparing a reference voltage having a predetermined level with a voltage level of the output terminal to generate a fuse state signal. | 11-04-2010 |
| 20110032010 | POWER UP SIGNAL GENERATION CIRCUIT AND METHOD FOR GENERATING POWER UP SIGNAL - A power up signal generation circuit transits a power up signal at a predetermined target voltage level by providing a predetermined hysteresis characteristic to the target voltage level of a power supply voltage corresponding to the power up signal. The power up signal generation circuit includes a first voltage detection unit that detects a first target voltage level of a power supply voltage to output a detection signal. The circuit also includes a second voltage detection unit that detects a second target voltage level of the power supply voltage in response to a power up signal to output a control signal, wherein the second target voltage level is lower than the first target voltage level. A power up signal drive unit of the circuit activates the power up signal in response to the detection signal and drives the power up signal in response to the control signal. | 02-10-2011 |
| 20110128971 | SEMICONDUCTOR DEVICE AND SIGNAL TRANSMISSION METHOD THEREOF - A semiconductor device having a plurality of transmission lines for transmitting a plurality of signals includes: a first transmission line configured to transmit a first signal while maintaining a same phase of the first signal during an entire transmission duration; and a second transmission line positioned adjacent to the first transmission line and configured to transmit a second signal while inverting a phase of the second signal during a first duration of the entire transmission duration. | 06-02-2011 |
| 20110140765 | INTERNAL NEGATIVE VOLTAGE GENERATION DEVICE - An internal negative voltage generation device includes a first internal negative voltage generation block configured to generate a first internal negative voltage which is lower than a ground voltage; a second internal negative voltage generation block configured to generate a second internal negative voltage according to the first internal negative voltage, the second internal negative voltage being higher than the first internal negative voltage and lower than the ground voltage; and an initial driving block configured to additionally drive a second internal negative voltage terminal to the first internal negative voltage during an initial set time interval of an active operation time interval. | 06-16-2011 |
