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Chang-Han

Chang-Han Chen, Xinpu Township TW

Patent application numberDescriptionPublished
20120012886LIGHT EMITTING DIODE, FRAME SHAPING METHOD THEREOF AND IMPROVED FRAME STRUCTURE - A single material tape is shaped into first, second and third frames isolated from and disposed opposite each other, and a press forming process is performed to thin bottoms of first and second wire-bonding sectors extending from the first and second frames. The thickness of each of the first and second wire-bonding sectors is smaller than that of the third frame, so that the thicker third frame can be exposed out of a glue body to achieve the better dissipation effect, and at least one side surface between the two frames isolated from and disposed opposite each other is formed with a slot portion. When the frame is applied to the light emitting diode and fixed to the glue body, the slot portion can increase the bonding property between the frame and the glue body, and the structural strength therebetween can be increased.01-19-2012

Chang-Han Choi, Gyeonggi-Do KR

Patent application numberDescriptionPublished
20090175072PHASE-CHANGE RANDOM ACCESS MEMORY DEVICES AND RELATED METHODS OF OPERATION - A phase-change random access memory (PRAM) device includes a plurality of banks, a plurality of column redundancy cell arrays, and a plurality of column redundancy write drivers. Each of the plurality of column redundancy cell arrays corresponds to at least one of the banks. Each of the plurality of column redundancy write drivers corresponds to at least one of the column redundancy cell arrays. The column redundancy write drivers are configured to transmit respective redundancy test data to the corresponding ones of the column redundancy cell arrays in response to a test control signal, which may be activated in response to each program pulse for writing data. Related test and access methods are also discussed.07-09-2009

Chang-Han Kim, Seoul KR

Patent application numberDescriptionPublished
20110013038APPARATUS AND METHOD FOR GENERATING IMAGE INCLUDING MULTIPLE PEOPLE - Provided is an apparatus and a method for generating an image including multiple people, in which images are photographed, face images are detected from each of the photographed images, a face score for each of the face images detected from the photographed images is calculated, it is determined whether each of the face scores calculated for each of the face images is at least equal to a predetermined threshold, and each of face images having a highest face score for each of the face images is synthesized, to output the synthesized image as a final image, in order to generate a most satisfactory photographed image for a user.01-20-2011
20110075933METHOD FOR DETERMINING FRONTAL FACE POSE - A method for determining a frontal face pose by using the symmetry of a face including detecting a face region in an image, detecting an eye region in the detected face region, normalizing the face region, analyzing the symmetry in the normalized face region, and determining whether a face pose is a frontal face pose based on an analysis of the symmetry.03-31-2011

Chang-Han Kim, Suwon-Si KR

Patent application numberDescriptionPublished
20100134899WIDE ANGLE ZOOM LENS - A wide angle zoom lens system in a three lens group N-P-P configuration wherein the first lens group, the second lens group, and the third lens group are arranged in an order from an object side to an image side, and wherein, when variable power operation is performed from a wide angle to a telephoto position, the distance between the first lens group and the second lens group is reduced, and the second lens group is moved toward the object side, and the distance between the second lens group and the third lens group is increased, and wherein the zoom lens has a large view angle at the wide angle position.06-03-2010

Chang-Han Shim, Changwon-City KR

Patent application numberDescriptionPublished
20090283316CIRCUIT BOARD VIAHOLES AND METHOD OF MANUFACTURING THE SAME - Provided are a circuit board with a viahole and a method of manufacturing the same. The circuit board includes: a substrate formed of an insulating material; a conductive layer disposed on the substrate; a plated layer comprising nickel and disposed on the conductive layer; and a viahole passing through the substrate, the conductive layer, and the plated layer, wherein a crystal growth direction of nickel in the plated layer is parallel to a thickness-wise direction of the substrate.11-19-2009
20090283884LEAD FRAME, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE LEAD FRAME AND THE SEMICONDUCTOR PACKAGE - Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns; and a pre-plating layer formed on both upper and lower surfaces of the die pad and the lead patterns.11-19-2009
20100116528PRINTED CIRCUIT BOARD WITH MULTIPLE METALLIC LAYERS AND METHOD OF MANUFACTURING THE SAME - Provided is a printed circuit board (PCB) with multiple metallic layers and a method of manufacturing the PCB to improve adhesion between a metal film and a polymer film, on which a circuit pattern is formed. The PCB includes: a first metal film; a polymer film formed on one surface of the first metal film; and a second metal film, interposed between the first metal film and the polymer film, having a first surface facing the first metal film and a second surface facing the polymer film, wherein the second surface is rougher than the first surface.05-13-2010
20110079887LEAD FRAME AND METHOD OF MANUFACTURING THE SAME - A lead frame having improved connectivity with a molded portion and a method of manufacturing the lead frame are provided. The lead frame includes a die pad on which a semiconductor chip is to be disposed; at least one lead portion arranged to be connected to the semiconductor chip; and at least one plating layer formed on at least one of the at least one lead portion and the die pad, wherein a top surface of the at least one plating layer has an uneven portion having a first average surface roughness.04-07-2011

Patent applications by Chang-Han Shim, Changwon-City KR