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| 20090004370 | Metal Inks, Methods of Making the Same, and Methods for Printing and/or Forming Metal Films - Printable metal formulations, methods of making the formulations, and methods of coating or printing thin films from metal ink precursors are disclosed. The metal formulation generally includes one or more Group 4, 5, 6, 7, 8, 9, 10, 11, or 12 metal salts or metal complexes, one or more solvents adapted to facilitate coating and/or printing of the formulation, and one or more optional additives that form (only) gaseous or volatile byproducts upon reduction of the metal salt or metal complex to an elemental metal and/or alloy thereof. The formulation may be made by combining the metal salt(s) or metal complex(es) and the solvent(s), and dissolving the metal salt(s) or metal complex(es) in the solvent(s) to form the formulation. Thin films may be made by coating or printing the metal formulation on a substrate; removing the solvents to form a metal-containing precursor film; and reducing the metal-containing precursor film. | 01-01-2009 |
| 20090020829 | PRINTING OF CONTACT METAL AND INTERCONNECT METAL VIA SEED PRINTING AND PLATING - Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. The method of forming contacts includes depositing an ink of a silicide-forming metal onto an exposed silicon surface, drying the ink to form a silicide-forming metal precursor, and heating the silicide-forming metal precursor and the silicon surface to form a metal silicide contact. Optionally, the metal precursor ink may be selectively deposited onto a dielectric layer adjacent to the exposed silicon surface to form a metal-containing interconnect. Furthermore, one or more bulk conductive metal(s) may be deposited on remaining metal precursor ink and/or the dielectric layer. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects. A metal ink may be printed for contacts as well as for local interconnects at the same time, or in the alternative, the printed metal can act as a seed for electroless deposition of other metals if different metals are desired for the contact and the interconnect lines. This approach advantageously reduces the number of processing steps and does not necessarily require any etching. | 01-22-2009 |
| 20090085095 | Profile Engineered Thin Film Devices and Structures - The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch. | 04-02-2009 |
| 20090109035 | High Reliability Surveillance and/or Identification Tag/Devices and Methods of Making and Using the Same - The present invention relates to methods of making capacitors for use in surveillance/identification tags or devices, and methods of using such surveillance/identification devices. The capacitors manufactured according to the methods of the present invention and used in the surveillance/identification devices described herein comprise printed conductive and dielectric layers. The methods and devices of the present invention improve the manufacturing tolerances associated with conventional metal-plastic-metal capacitor, as well as the deactivation reliability of the capacitor used in a surveillance/identification tag or device. | 04-30-2009 |
| 20090137071 | High Reliability Surveillance and/or Identification Tag/Devices and Methods of Making and Using the Same - The present invention relates to methods of making capacitors for use in surveillance/identification tags or devices, and methods of using such surveillance/identification devices. The capacitors manufactured according to the methods of the present invention and used in the surveillance/identification devices described herein comprise printed conductive and dielectric layers. The methods and devices of the present invention improve the manufacturing tolerances associated with conventional metal-plastic-metal capacitor, as well as the deactivation reliability of the capacitor used in a surveillance/identification tag or device. | 05-28-2009 |
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| 20110320373 | PRODUCT CONVERSATIONS AMONG SOCIAL GROUPS - Conversations about products and product areas arise among users who also participate in social networks. These conversations often occur over generalized communications channels, such as email or social network messages, which may be unstructured and ephemeral. Such conversations may be promoted among the users of a social group (such as a highly interconnected set of users), and may be restricted to the members of the social group in order to promote reliable discussion and personalized recommendations. The social network may also store such conversations as a product review database that is searchable by members of the social group, evaluate the conversation to identify a consensus recommendation of a product in a product area or a consensus opinion of the social group about a product or recommendation, and compute an aggregated user rating of a product based on the user ratings of the product by various members of the social group. | 12-29-2011 |
| 20110320423 | INTEGRATING SOCIAL NETWORK DATA WITH SEARCH RESULTS - A user of a social network may submit a search query relating to one or more topics to a search engine indexing a set of data items, but the search results, while authoritative and informative, may be highly impersonal with respect to the user. Conversely, the user may search for social data items within the social network relating to the topics, and such social data items may be more highly personalized to the user, but may also be inaccurate or incomplete. Instead, the search query may be applied to both the search engine and the social network, and the selected search results and social data items may be integrated into a presentation featuring both authoritative and personalized information about the topics associated with the search query. | 12-29-2011 |
| 20110320441 | ADJUSTING SEARCH RESULTS BASED ON USER SOCIAL PROFILES - Many contemporary computing scenarios involve the submission by a user of a search query to be applied to a data set (such as a set of web pages indexed by a web search engine.) Additionally, many users participate in social networking and have generated a social profile, including demographic information, interests, and associations with other users who also have social profiles. It may be advantageous to improve the presentation of search results from search queries by adjusting the search queries according to a prediction of user interest of the user in the topics associated with respective search results, based on the information in the social profile of the user. For example, search results relating to topics in which the user or the user's friends have expressed an interest within the social network may be presented before other search results, thereby improving the relevance of the search results to the user. | 12-29-2011 |
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| 20110288941 | CONTEXTUAL CONTENT ITEMS FOR MOBILE APPLICATIONS - This specification describes technologies relating to content presentation. In general, one aspect of the subject matter described in this specification can be embodied in methods that include the actions of receiving a request to serve a content item to an application on a mobile device; identifying a context associated with the application, the context being derived from an application description page for the application and one or more pages linking to the application description page, the context comprising one or more keywords associated with the application; selecting a content item, from a collection of content items, using the context; and serving the selected content item to the application on the mobile device. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. | 11-24-2011 |
| 20110307323 | CONTENT ITEMS FOR MOBILE APPLICATIONS - This specification relates to content presentation. In general, one aspect of the subject matter described in this specification can be embodied in methods that include actions of receiving a request to serve a content item to an application on a mobile device, the application being associated with one or more categories; for each of a plurality of content items in a collection of content items, identifying a performance signal for the content item, the performance signal representing the performance of the content item when served to one or more other mobile devices running the application and one or more other applications associated with one of the one or more categories; selecting, using one or more processors, a first content item from the plurality of content items based on the performance signals of the plurality of content items; and providing the first content item to the application on the mobile device. | 12-15-2011 |
| 20110321167 | AD PRIVACY MANAGEMENT - In general, this specification relates to content presentation. In general, one aspect of the subject matter described in this specification can be embodied in methods that include the actions of receiving a privacy request from a mobile device, the privacy request including an encoded device identifier; authenticating the request; decoding the device identifier; retrieving mobile device advertising data associated with the decoded device identifier; and applying the privacy request to the mobile device advertising data. Other embodiments of this aspect include corresponding systems, apparatus, and computer program products. | 12-29-2011 |
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| 20100059783 | Light Emitting Chip Package With Metal Leads For Enhanced Heat Dissipation - A light emitting chip package includes a planar substrate, an LED die mounted on the substrate, and one or more relatively wide and thick metal leads to serve as a low thermal resistance path. The substrate comprises a chip mounting area and a wire bond area on a dielectric body. The LED die is seated on the chip mounting area and electrically connected to the wire bonding area. The metal leads are attached to the substrate and form terminals for external connection. At least one metal lead is connected to the chip mounting area to serve as a low thermal resistance path between the chip mounting area and an external heat sink. | 03-11-2010 |
| 20100072582 | Semiconductor Device and Method of Electrically Connecting a Shielding Layer to Ground Through a Conductive Via Disposed in Peripheral Region Around Semiconductor Die - A semiconductor device is made by mounting a plurality of semiconductor die to a substrate, depositing an encapsulant over the substrate and semiconductor die, forming a shielding layer over the semiconductor die, creating a channel in a peripheral region around the semiconductor die through the shielding layer, encapsulant and substrate at least to a ground plane within the substrate, depositing a conductive material in the channel, and removing a portion of the conductive material in the channel to create conductive vias in the channel which provide electrical connection between the shielding layer and ground plane. An interconnect structure is formed on the substrate and are electrically connected to the ground plane. Solder bumps are formed on a backside of the substrate opposite the semiconductor die. The shielding layer is connected to a ground point through the conductive via, ground plane, interconnect structure, and solder bumps of the substrate. | 03-25-2010 |
| 20100148344 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INPUT/OUTPUT EXPANSION - An integrated circuit package system includes: forming a base stacking package including: fabricating a base substrate, mounting an integrated circuit on the base substrate, positioning an input/output expansion substrate, having access ports around an inner array area, over the integrated circuit, and injecting a molding compound on the base substrate, the integrated circuit, and the input/output expansion substrate; and mounting a top package on the input/output expansion substrate. | 06-17-2010 |
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| 20090089546 | Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache - In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads. | 04-02-2009 |
| 20090169214 | UNIFIED OPTICAL CONNECTOR ARCHITECTURE - A system, device, and method are disclosed. In one embodiment the system includes an optical link and a peripheral device optically coupled to the optical link. The system also includes a host controller, such as a graphics, network, or I/O controller. The system also includes a unified optical connector port, which is optically coupled to the optical link and electrically coupled to the first host controller. The port has a wavelength allocation unit that can allocate an optical wavelength for an optical signal that is utilized to communicate with the peripheral device. The port also includes an electrical-to-optical transmission unit capable of converting an electrical signal, received from the host controller, to the optical signal that was allocated at the first optical wavelength. The electrical-to-optical transmission unit is also capable of transmitting one or more data packets within the first optical signal to the peripheral device across the optical link. | 07-02-2009 |
| 20090172185 | UNIFIED CONNECTOR ARCHITECTURE - A system, device, and method are disclosed. In one embodiment the system includes a first host controller that utilizes a first protocol. The system also includes a second host controller that utilizes a second protocol. The system also includes a unified connector port. Finally, the system includes a router that is coupled to the first host controller, the second host controller, and the unified connector port. The router is functionally capable of encapsulating a physical layer packet from the first host controller into a first unified connector protocol frame and then transmits the new first frame to the unified connector port. The router is also capable of encapsulating a physical layer packet that it receives from the second host controller into a second unified connector protocol frame and then transmits the second frame to the unified connector port. The first and second protocols are not the same protocol. | 07-02-2009 |
| 20100049885 | Unified multi-transport medium connector architecture - A device, method, and system are disclosed. In one embodiment the device includes a router to transmit data packets between multiple host controllers and one or more peripheral devices. The router can receive a data packet from a host controller and transmit the data packet to a peripheral device across a data transmission path. The peripheral device is coupled to the first data transmission path through a first universal multi-transport medium (UMTM) connector. The connector includes an optical coupling capable of transporting the first data packet within an optical signal and an electrical coupling capable of transporting the first data packet within an electrical signal. | 02-25-2010 |
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| 20100077035 | Optimized Polling in Low Resource Devices - Methods and systems for optimizing server polling by a mobile client are described, thereby allowing mobile terminals to conserve battery life by more efficiently using resources such as the processor and transceiver in the mobile terminal. A broker system may be used to minimize wireless communication traffic used for polling. A broker stub intercepts server polling messages at the client, multiplexes the sever requests together, and forwards the multiplexed message to a broker skeleton that de-multiplexes and forwards the messages as appropriate. Polling may also be dynamically adapted based on user behavior, or a server guard may be used to monitor changes to data, and notify a client to poll its respective server when the server guard detects new or updated data on that server for that client. | 03-25-2010 |
| 20110081922 | METHOD AND APPARATUS FOR PROVIDING LOCATION BASED SERVICES USING CONNECTIVITY GRAPHS BASED ON CELL BROADCAST INFORMATION - An approach is provided for providing location based services using connectivity graphs based on cell broadcast information. A plurality of cell broadcast message identifiers are caused to be received. Cell broadcast message identifiers are respectively associated with a plurality of cells. A connectivity graph specifying relationships among the cells is generated for providing a location based service. | 04-07-2011 |
| 20110151898 | METHOD AND APPARATUS FOR GROUPING POINTS-OF-INTEREST ACCORDING TO AREA NAMES - An approach is provided for crowd sourcing and grouping points-of-interest based on cell broadcast message information. Reception of a message from a mobile terminal is caused, at least in part. The message specifies point-of-interest information and an associated area name corresponding to one of a plurality of cells of a communication network. The message is parsed to determine the point-of-interest information and the associated area name. A connectivity graph specifying relationships among the cells is selectively updated with the point-of-interest information. | 06-23-2011 |
| 20110208810 | Optimized Polling in Low Resource Devices - Methods and systems for optimizing server polling by a mobile client are described, thereby allowing mobile terminals to conserve battery life by more efficiently using resources such as the processor and transceiver in the mobile terminal A broker system may be used to minimize wireless communication traffic used for polling. A broker stub intercepts server polling messages at the client, multiplexes the sever requests together, and forwards the multiplexed message to a broker skeleton that de-multiplexes and forwards the messages as appropriate. Polling may also be dynamically adapted based on user behavior, or a server guard may be used to monitor changes to data, and notify a client to poll its respective server when the server guard detects new or updated data on that server for that client. | 08-25-2011 |
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| 20080269548 | DYNAMIC AND ADJUSTABLE SUPPORT DEVICES - The present invention relates generally to dynamic and/or adjustable support devices, methods of providing dynamic and/or adjustable support to target tissues, and kits comprising these devices. These devices may have particular utility in providing support to the urethra. The dynamic support devices generally comprise at least one attachment member for attachment to bodily tissue, and at least one expandable member capable of assuming an unexpanded configuration and an expanded configuration. The adjustable support devices generally comprise at least one attachment member for attachment to bodily tissue, and at least one shape-changing portion that is capable of assuming first and second configurations, each with different shapes. Additionally, the dynamic support devices may comprise features of the adjustable support devices, and vice versa. | 10-30-2008 |
| 20090082617 | METHODS AND DEVICES FOR SUPPORTING, ELEVATING, OR COMPRESSING INTERNAL STRUCTURES - The present invention relates generally to dynamic support devices, methods of providing dynamic support to target tissues, and kits comprising these devices. These devices may have particular utility in providing support to the urethra. The dynamic support devices generally comprise at least one attachment member for attachment to bodily tissue, and at least one support member, where the device capable of assuming a first configuration and a second configuration. The dynamic support devices may be configured to support a target tissue when the device is in its second configuration. The support member may comprise one or more rotating components, one or more deformable components, one or more sliding components, or a combination thereof. | 03-26-2009 |
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| 20090245013 | Sequential storage circuitry for an integrated circuit - Sequential storage circuitry is provided for an integrated circuit, comprising input circuitry, a storage structure, and output circuitry. The input circuitry receives an input data value to the sequential storage circuitry, and generates an internal data value. The input circuitry receives a first control signal which when asserted causes it to generate as the internal data value an inverted version of the input data value, and which when not asserted causes the input circuitry to generate as the internal data value the input data value. The storage structure then stores an indication of the internal data value. The output circuitry generates, from the indication of the internal data value stored in the storage structure, an output data value for outputting from the sequential storage circuitry. More particularly, the output circuitry receives a second control signal derived from the first control signal, which causes the output circuitry to generate as said output data value an inverted version of the internal data value in the event that the input circuitry generated as the internal data value an inverted version of the input data value, and otherwise generates as the output data value the internal data value. Such a mechanism provides a simple and effective technique for annealing stress build-up within the storage structure, as for example may arise as a result of the NBTI phenomenon. The technique of the present invention can be also be used for other purposes, for example to improve security of the data held within such a sequential storage circuitry. | 10-01-2009 |
| 20090249175 | Single Event Upset error detection within sequential storage circuitry of an integrated circuit - Sequential storage circuitry for a integrated circuit is provided, comprising a first storage element, a second storage element and an additional storage element. The first storage element stores, during a first phase of a clock signal, a first indication of an input data value received by the sequential storage circuitry. The second storage element is coupled to an output of the first storage element, and stores a second indication of the input data value during a second phase of the clock signal. The additional storage element is driven by a pulse signal derived from the clock signal, and is arranged on occurrence of that pulse signal to store a third indication of the input data value. Error detection circuitry is then provided for detecting a single event upset error in either the first storage element or the second storage element. In particular, during the first phase of the clock signal, the error detection circuitry detects the single event upset error in the first storage element if there is a difference in the input data value as indicated by the first indication and the third indication. Further, during the second phase of the clock signal, the error detection circuitry detects a single event upset error in the second storage element if there is a difference in the input data value as indicated by the second indication and the third indication. Such an arrangement provides a simple mechanism for detecting soft errors in both the first storage element and the second storage element using only one additional storage element. | 10-01-2009 |
| 20100088565 | Correction of single event upset error within sequential storage circuitry of an integrated circuit - Sequential storage circuitry for an integrated circuit is disclosed that comprises storage circuitry comprising: a first storage element for storing, during a first phase of a clock signal, a first indication of an input data value received by said sequential storage circuitry; a second storage element coupled to an output of said first storage element, for storing a second indication of said input data value during a second phase of said clock signal; and error detection circuitry for detecting a single event upset error in any of said first and second storage elements comprising: two additional storage elements for storing third and fourth indications of said input data value respectively in response to a pulse signal derived from said clock signal; comparison circuitry for comparing said third and fourth indications of said input data value; and further comparison circuitry for comparing during a first phase of said clock signal said first indication and at least one of said third and fourth indications, and for comparing during a second phase of said clock signal said second indication and at least one of said third and fourth indications; and output circuitry for correcting any detected errors in said storage circuitry and for outputting an output value; said output circuitry being responsive to no match by said comparison circuitry to output said first indication during a first phase of said clock signal and said second indication during said second phase of said clock signal, and said output circuitry being responsive to a match by said comparison circuitry to output a value in dependence upon comparisons performed by said further comparison circuitry; said output circuitry being responsive to a match by said further comparison circuitry during a first phase of said clock signal to output said first indication during said first clock cycle and to a no match to output an inverted value of said first indication; and said output circuitry being responsive to a match by said further comparison circuitry during a second phase of said clock signal to output said second indication during said second phase of said clock signal and to a no match to output an inverted value of said second indication. | 04-08-2010 |
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| 20110004813 | Low overhead circuit and method for predicting timing errors - Data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a data input, a data output and a processing path arranged between the data input and the data output. The processing path comprises: a plurality of synchronisation circuits for capturing and transmitting the data in response to a clock signal; and a plurality of combinational circuits arranged between the synchronisation circuits for processing the data. The data processing circuitry further comprises: a plurality of retention circuits for storing data in a low power mode, the plurality of retention circuits being arranged in parallel with the processing path; and at least one potential error detecting circuit for determining during processing of the data if the data signal pending at an input to one of the plurality of synchronisation circuits is stable during a predetermined time prior to capture of the data and for signalling a potential error if the data input is determined to be unstable during the predetermined time. The at least one potential error detecting circuit comprising: a potential error detecting path for transmitting the data signal pending at the input of the one of the plurality of synchronisation circuits to one of the retention circuits the potential error detecting path comprising delay circuitry for delaying the data signal such that the data signal arrives at the retention circuit the predetermined time after it arrives at the synchronisation circuit; and comparison circuitry for comparing a value of the data signal captured by one of the synchronisation circuits with a value of the data signal captured by a corresponding one of the retention circuits, the comparison circuitry being configured to signal a potential error in response to detecting a difference in the captured data values. | 01-06-2011 |
| 20110063932 | Boosting voltage levels applied to an access control line when accessing storage cells in a memory - A semiconductor memory storage device is disclosed, the memory comprises: a plurality of storage cells for storing data; at least two access control lines each for controlling access to a respective at least one of the plurality of storage cells; at least two access control circuits each for controlling a voltage level supplied to a corresponding one of the at least two access control lines in response to an access request, the at least two access control circuits each comprising a capacitor and switching circuitry; routing circuitry for routing the access request and a boost signal to a selected one of the at least two access control circuits in dependence upon an address associated with the access request; wherein the at least two access control circuits are each responsive to: receipt of the access request from the routing circuitry to connect the selected access control line to a supply voltage; and receipt of the boost signal from the routing circuitry to disconnect the supply voltage from the access control line and to couple the boost signal to the access control line through the capacitor of the access control circuit to provide a boost to a voltage level on the access control line. | 03-17-2011 |
| 20110085391 | Memory with improved read stability - A static random access memory is disclosed. The SRAM comprises: at least one data line for transferring data to and from the memory and at least one reset line; a plurality of storage cells each being arranged for connection to the at least one data line and the at least one reset line, each storage cell comprising: an asymmetric feedback loop, the feedback loop comprising a first access node for holding a data value when the feedback loop stores the data value and a second access node for holding a complementary version of the data value when the feedback loop stores the data value; an access device for selectively providing a connection between the at least one data line and the first access node; a reset device for selectively providing a connection between the at least one reset line and the second access node; the memory further comprising: data access control circuitry for generating control signals in response to data access requests for independently controlling the access device and the reset device to provide the connections; wherein: the data control circuitry is configured to: generate a data access control signal to trigger the access device to provide the connection between the first access node and the at least one data line in response to a write request to write a predetermined value to the storage cell, and in response to a read request to read a stored value from the storage cell; and generate a reset control signal to trigger the reset device to provide the connection between the at least one reset line and the second access node in response to a write request to write the complementary predetermined value to the storage cell. | 04-14-2011 |
| 20110261633 | Memory with improved data reliability - An integrated circuit is provided comprising at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of bit cells. Each column of the memory cells is coupled to one of a plurality of bit lines. Each row of the memory cells is coupled to one of a plurality of word lines, to control coupling of that row of memory cells to the plurality of bit lines in dependence on a respective word line signal. Word line driver circuitry is configured to group together the word lines of at least three rows of memory cells, such that the word lines of the at least three rows of memory cells share a common word line signal. Thus in a write operation a written data value written into the array of memory cells is written to at least three memory cells having a shared bit line. Read circuitry is coupled to the plurality of bit lines, configured such that in a read operation, in which the at least three memory cells are all coupled to the shared bit line by means of the common word line signal, a read data value is determined in dependence on a voltage of the shared bit line, dependent on data values stored in the at least three memory cells. If, at a time of the read operation, one of the at least three memory cells holds a complement value of the written data value, the voltage of the shared bit line nonetheless has a value such that the read data value is determined with the same value as the written data value. | 10-27-2011 |
