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Chan, Hsinchu City
Cheng-Sheng Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100125688 | EXTERNAL DEVICE HAVING A VIRTUAL STORAGE DEVICE - An external device includes a bridge and a storage device. The bridge is connected to a host according to a first data transmission interface so as to convert data of the host from the first data transmission interface to a second data transmission interface. The bridge includes a memory unit and a control unit. The memory unit stores a virtual device datum. The control unit generates a virtual storage device in the host according to the virtual device datum. The storage device is connected to the bridge for storing the data of the host according to the second data transmission interface. | 05-20-2010 |
| 20100180080 | EXTERNAL STORAGE DEVICE HAVING A SELF-CONTAINED SECURITY FUNCTION - An external storage device includes a storage device and a bridge. The storage device stores data transmitted from a computer host. The bridge includes a memory unit and a control unit. The memory unit stores a virtual device datum, and the virtual device datum includes an application program. The control unit generates a virtual storage device in the computer host according to the virtual device datum, and executes a security function of the storage device according to the application program. | 07-15-2010 |
Chien-Ling Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090042395 | Spacer process for CMOS fabrication with bipolar transistor leakage prevention - A two-step spacer etch is used for the formation of a spacer in CMOS fabrication. A dry etch is first applied to remove part of the spacer material on the silicon substrate and leave a thin layer of the spacer material remained on the silicon substrate. Then, a wet etch is applied to completely remove the thin layer of the spacer material on the silicon substrate. The wet etch has good etch selectivity between the spacer material and silicon, and thus will not damage the surface of the silicon substrate when the spacer is formed. Therefore, the BJT on the silicon substrate is prevented from junction leakage. | 02-12-2009 |
Chien-Tai Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110210393 | DUAL EPITAXIAL PROCESS FOR A FINFET DEVICE - A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step. | 09-01-2011 |
| 20110295539 | METHOD AND APPARATUS FOR MEASURING INTRA-DIE TEMPERATURE - A method for measuring the intra-die temperature of a wafer with a fast response time is described. The method includes providing a wafer in a thermal process chamber, radiating the wafer in a first predetermined radiation range to heat the wafer to a predetermined temperature range for a predetermined time, receiving the radiation reflected from a die area while the wafer is being heated and detecting reflected radiation having a second predetermined radiation range, and determining a temperature of the die area by a processor being responsive to the detected second predetermined radiation range. | 12-01-2011 |
Chien-Yu Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090323768 | SPREAD SPECTRUM CLOCK SIGNAL GENERATOR - A spread spectrum clock signal generator for spreading an input clock signal into an output clock signal includes a clock signal delay chain for delaying the input clock signal into a delay clock signal group having a plurality of delay clock signals, a modulation controller for outputting a counter clock signal control signal, a clock signal selection circuit for selecting, from the delay clock signal group, a modulation clock signal group having a plurality of modulation clock signals, a programmable counter for generating a counting value according to a counter clock signal, and a clock signal output unit for combining the modulation clock signals into the output clock signal according to the counting value, and further generating the counter clock signal, outputted to the programmable counter, according to the counter clock signal control signal. | 12-31-2009 |
| 20100110115 | Frame Rate Control Method and Display Device Using the Same - A frame rate control (FRC) method is provided for driving a number of pixels according to a number of pixels data. The pixels include a number of first color sub-pixels. In this method, the dithering process is performed to the pixels data in two frames according to two basic matrixes respectively. In one of the two frames, the numbers of the first color sub-pixels, driven by the positive pixel voltages and the negative pixel voltages and to which the dithering process has been performed, are the same in substantiality. Further, in the other of the two frames, the numbers of the first color sub-pixels, driven by the positive pixel voltages and the negative pixel voltages and to which the dithering process has been performed, are also the same in substantiality. | 05-06-2010 |
Chi-Hung Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100317313 | DUAL-BAND COUPLER UNIT AND DUAL-BAND COUPLER THEREOF AND RECEIVER THEREOF - A dual-band coupler unit is provided. The dual-band coupler unit includes a first coupled line, a second coupled line, a short transmission line, a first transmission line, and a second transmission line. The first coupled line and the second coupled line are substantially in parallel with each other, and are substantially of the same length. One end of the short transmission line is connected to one end of the first coupled line, and the other end of the short transmission line is connected to one end of the second coupled line. One end of the first transmission line is connected to the other end of the first coupled line, and one end of the second transmission line is connected to the other end of the second coupled line. | 12-16-2010 |
| 20110309894 | PLANAR ASYMMETRIC CROSSOVER COUPLER - A planar asymmetric crossover coupler has a first branch to a seventh branch. The first branch to the fourth branch form a first region having a first port and a fourth port. The fourth branch to the seventh branch form a second region having a second port and a third port. The characteristic impedance of each branch is determined according to the load impedance and power distribution ratio of each port. | 12-22-2011 |
Chun-Kai Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110179870 | DUAL-AXIS ACCELERATION DETECTION ELEMENT - A dual-axis acceleration detection element comprises a first detection element, a second detection element and a stationary unit. The first detection element is movable relative to the second detection element. The second detection element is movable relative to the stationary unit. The relative movements take place on different axes to detect acceleration on two different axes. The first detection element and the second detection element are interposed by corresponding detection electrodes, and the second detection element and the stationary unit also are interposed by other corresponding detection electrodes. Hence when the relative movements occur among the first and second detection elements and the stationary unit, overlapped areas of the detection electrodes change to generate and output a capacitance difference, thereby acceleration alteration can be detected. | 07-28-2011 |
| 20120025334 | MEMS CAPACITIVE MICROPHONE - The present invention discloses an MEMS capacitive microphone including a rigid diaphragm arranged on an elastic element. When a sound wave acts on the rigid diaphragm, the rigid diaphragm is moved parallel to a normal of a back plate by elasticity of the elastic element. Thereby the variation of the capacitance is obtained between the rigid diaphragm and the back plate. | 02-02-2012 |
| 20120027235 | MEMS CAPACITIVE MICROPHONE - The present invention discloses an MEMS capacitive microphone, which comprises a supporting portion and a diaphragm, wherein the supporting portion supports the central portion of the diaphragm to facilitate releasing the residual stress of the diaphragm generated in the thermal fabrication process. Thereby is maintained the flatness of the diaphragm and promoted the precision of sensing capacitance. | 02-02-2012 |
Hing-Yuen Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100021551 | PROCESS FOR PREPARING NANOPARTICLES OF CHITOSAN IN WATER PHASE - A method for preparing chitosan nanoparticles in water phase is provided. The method comprises the following steps: | 01-28-2010 |
Kuei-Ti Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090002114 | INTEGRATED INDUCTOR - An integrated inductor has a winding. The winding includes a first level metal layer inlaid in a first dielectric layer, a second level metal layer inlaid in a second dielectric layer above the first dielectric layer, and a first line-shaped via structure inlaid in a slot of a third dielectric layer interposed between the first and second dielectric layers for interconnecting the first and second level metal layers. | 01-01-2009 |
| 20090261937 | INTEGRATED INDUCTOR - An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well. | 10-22-2009 |
| 20100295150 | SEMICONDUCTOR DEVICE WITH OXIDE DEFINE DUMMY FEATURE - A semiconductor device includes a substrate, an inductor wiring pattern on the substrate, and at least one oxide define (OD) dummy feature disposed in the substrate under the inductor wiring pattern. | 11-25-2010 |
| 20110133308 | SEMICONDUCTOR DEVICE WITH OXIDE DEFINE PATTERN - A semiconductor device includes a substrate; an inductor wiring pattern overlying the substrate, wherein the inductor wiring pattern is formed in an inductor-forming region; a plurality of shielding patterns between the inductor wiring pattern and the substrate within the inductor-forming region; and at least one first oxide define (OD) pattern disposed in the substrate or between the inductor wiring pattern and the substrate. | 06-09-2011 |
Pei-Chen Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110187633 | DISPLAY CAPABLE OF RESTRAINING RIPPLE OF COMMON VOLTAGE - A display including a display panel and a compensation circuit is provided. The display panel includes a plurality of common lines for transmitting a common voltage; a plurality of scan lines; a plurality of data lines disposed substantially perpendicular to the scan lines; a plurality of pixels arranged in an array and each electrically connected to the corresponding data line, scan line, and common line; and a sensing line crossing over at least one first data line among the data lines. A parasitic capacitor is formed between the first data line and the sensing line. The compensation circuit is electrically connected to the sensing line and the common lines. The compensation circuit generates a compensation signal for the common lines according to a coupling signal induced by the parasitic capacitor between the first data line and the sensing line so as to restrain ripple of the common voltage. | 08-04-2011 |
Shu-Chun Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080280448 | METHOD FOR MANUFACTURING GATE OXIDE LAYER WITH DIFFERENT THICKNESSES - A method of manufacturing gate oxide layers with different thicknesses is disclosed. The method includes that a substrate is provided first. The substrate has a high voltage device region and a low voltage device region. Then, a high voltage gate oxide layer is formed on the substrate. Afterwards, a first wet etching process is performed to remove a portion of the high voltage gate oxide layer in the low voltage device region. Then, a second wet etching process is performed to remove the remaining high voltage gate oxide layer in the low voltage device region. The etching rate of the second wet etching process is smaller than that of the first wet etching process. Next, a low voltage gate oxide layer is formed on the substrate in the low voltage device region. | 11-13-2008 |
Te-Jung Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100149063 | DUAL-FREQUENCY ANTENNA - A dual-frequency antenna includes a substrate, a ground layer, a plurality of signal feed portions, at least one first radiation portion, a plurality of second radiation portions, a plurality of first signal transmission lines, a plurality of second signal transmission lines, a plurality of first filters, and a plurality of second filters. The signal feed portions are disposed between the first radiation portions and the second radiation portions that are disposed on the first surface of the substrate in a staggered manner. The first signal transmission lines and the second signal transmission lines are respectively used to connect the signal feed portions with the first radiation portions and the second radiation portions. The first filters and the second filters are respectively disposed on the first signal transmission lines and the second signal transmission lines. The dual-frequency antenna is applicable for providing broadband and high gain features. | 06-17-2010 |
Wei-Chia Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110095822 | VARIABLE-GAIN LOW NOISE AMPLIFIER - A highly linear variable-gain low noise amplifier is a cascode amplifier. The cascode amplifier includes a gain control circuit, a load circuit, a current steering circuit and an input circuit. The gain control circuit is used for receiving a gain adjusting voltage, thereby generating a resistance adjusting signal and a current steering control signal. The load circuit includes plural variable resistors. The resistances of the variable resistors are adjusted according to the resistance adjusting signal. The current steering circuit is connected to the load circuit through plural current paths for adjusting a current ratio between the plural current paths according to the current steering control signal. The current steering circuit has differential signal output terminals. The input circuit is connected to the current steering circuit. The input circuit has differential signal input terminals. | 04-28-2011 |
Wei Ting Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100328442 | HUMAN FACE DETECTION AND TRACKING DEVICE - A human face detection device includes a photosensitive element, a human face detection unit, and a skin color threshold generation unit. The photosensitive element is used for capturing a first image containing a first human face block. The human face detection unit compares the first image with at least one human face feature, so as to detect the first human face block. The skin color threshold generation unit is used for updating a skin color threshold value according to the detected first human face block. The skin color threshold value is used for filtering the first image signal to obtain a candidate region, the human face detection unit compares the candidate region with the at least one human face feature to obtain the first human face block, and the skin color threshold value determines whether the first human face block detected by the human face detection unit is correct. | 12-30-2010 |
| 20100328498 | SHOOTING PARAMETER ADJUSTMENT METHOD FOR FACE DETECTION AND IMAGE CAPTURING DEVICE FOR FACE DETECTION - A shooting parameter adjustment method for face detection includes (A) acquiring an image; (B) dividing the image into a plurality of blocks, and calculating a brightness value of each of the blocks; (C) selecting at least one of the plurality of blocks, and adjusting a shooting parameter according to the brightness value of the selected block; and (D) acquiring another image according to the shooting parameter, and performing a face detection procedure with the another image. The shooting parameter adjustment method can automatically adjust a shooting parameter of an image capturing device according to brightness of different blocks in an image. Therefore, by using this method, the brightness of a face, no matter being too high or too low, can be adjusted to a value suitable for face detection, so as to improve the accuracy of the face detection procedure. | 12-30-2010 |
| 20100329518 | DYNAMIC IMAGE COMPRESSION METHOD FOR HUMAN FACE DETECTION - A dynamic image compression method for human face detection includes the following steps. An original image is acquired. The image is divided into a plurality of blocks. A first brightness and a plurality of gradient values of each block are calculated. A second brightness of each block is calculated according to a brightness transformation function and the first brightness. A reconstruction image is generated according to the second brightness and the plurality of gradient values of each block. Human face detection is performed according to the reconstruction image. Therefore, gradient values within an original square are. When the human face detection process is performed through gradient direction information, a success rate of detection is greatly increased. | 12-30-2010 |
Wing Chor Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110220973 | JUNCTION-FIELD-EFFECT-TRANSISTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A junction-field-effect-transistor (JFET) device includes a substrate of a first-type impurity, a first well region of a second-type impurity in the substrate, a pair of second well regions of the first-type impurity separated from each other in the first well region, a third well region of the first-type impurity between the pair of second well regions, a first diffused region of the second-type impurity between the third well region and one of the second well regions, and a second diffused region of the second-type impurity between the third well region and the other one of the second well regions. | 09-15-2011 |
| 20110291187 | Double Diffused Drain Metal-Oxide-Semiconductor Devices with Floating Poly Thereon and Methods of Manufacturing The Same - A metal-oxide-semiconductor (MOS) device is disclosed. The MOS device includes a substrate of a first impurity type, a diffused region of a second impurity type in the substrate, a patterned first dielectric layer including a first dielectric portion over the diffused region, a patterned first conductive layer on the patterned first dielectric layer, the patterned first conductive layer including a first conductive portion on the first dielectric portion, a patterned second dielectric layer including a second dielectric portion that extends on a first portion of an upper surface of the first conductive portion and along a sidewall of the first conductive portion to the substrate; and a patterned second conductive layer on the patterned second dielectric layer, the patterned second conductive layer including a second conductive portion on the second dielectric portion. | 12-01-2011 |
Yi-Sung Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120039157 | METHOD FOR RECORDING CRITICAL PATTERNS WITH DIFFERENT MARK LENGTHS ONTO OPTICAL STORAGE MEDIUM AND RELATED CONTROLLER THEREOF - An exemplary method for recording a first mark with a first length and a second mark with a second length onto an optical storage medium includes: when recording of the first mark requires a power transition from a first laser power level to a second laser power level, making a specific control signal have a logic transition from a low logic value to a high logic value and other control signals have no logic transition; and when recording of the second mark requires a power transition from a third laser power level to a fourth laser power level, making the specific control signal have the logic transition from the low logic value to the high logic value and other control signals have no logic transition. | 02-16-2012 |
Yung-Ta Chan, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110158108 | ETHERENT PHYSICAL LAYER TEST SYSTEM AND METHOD - An Ethernet physical layer test system and method, wherein a signal pattern generator is utilized to generate repeatedly a signal pattern frame required by the test items of the Ethernet physical layer according to a transmission procedure of a medium access controller; meanwhile, the signal pattern generator generates a control signal for switching a multiplexer, so as to control the transmission of a signal pattern frame. The Ethernet physical layer receives the signal pattern frame and outputs a test packet to a measurement instrument via a twisted-pair, for testing and analyzing quality of signals output by the Ethernet physical layer. Through the application of this Ethernet physical layer test system and method, the time required for testing the Ethernet physical layer can be effectively reduced, thus simplifying the complexity of an algorithm in testing the Ethernet physical layer. | 06-30-2011 |