Patent application number | Description | Published |
20080199745 | METHOD OF DRIVING HEATING UNIT FOR REFORMER, AND REFORMER AND FUEL CELL SYSTEM INCLUDING THE SAME - A method of driving a heating unit for a fuel cell reformer, a reformer applied with the method for driving the heating unit, and/or a fuel cell system including the reformer. The method includes: supplying an oxidant to the heating unit and absorbing the oxidant by a fuel oxidizing catalyst of the heating unit; supplying a fuel at an excessive amount to the heating unit and absorbing the fuel by the fuel oxidizing catalyst of the heating unit; and supplying the fuel and the oxidant to the heating unit at a stoichiometric ratio of the fuel to the oxidant ranging from 1:1 to 2:1, wherein the heating unit generates heat through an oxidizing catalyst reaction between the fuel and the oxidant. | 08-21-2008 |
20080206613 | Reformer for fuel cell, and fuel cell system comprising the same - A reformer for a fuel cell system includes a heating source for generating heat by a reaction of a fuel and an oxidant using an oxidizing catalyst, and a reforming reaction part for generating hydrogen by a reforming catalyst reaction. The oxidizing catalyst includes a solid acid, including a strong acid ion and an inorganic oxide, and a platinum-based metal. The reformer for a fuel cell system can start a fuel oxidation catalyst reaction at a low temperature with the heating source having a simplified structure. | 08-28-2008 |
20080241019 | REACTION VESSEL AND REACTION DEVICE - Provided is a reaction vessel for a fuel cell, and more particularly to a reaction vessel exhibiting improved thermal efficiency, and a reaction device for a steam reforming reaction for a fuel cell. The reaction device includes a cylindrical reaction catalyst chamber on which a target reaction catalyst for a predetermined target reaction is disposed; and a tubular oxidation catalyst chamber surrounding the reaction catalyst chamber, comprising an oxidation reaction catalyst therein. The reaction device according features an increased contact area between catalyst and gas, and rapidly heating of the gas in contact with the catalyst to a desired reaction temperature. | 10-02-2008 |
20100226023 | LENS BARREL AND OPTICAL DEVICE WITH THE SAME - To easily combine a lens holding barrel with a mobile barrel, or separate the lens holding barrel from the mobile barrel, and to protect the lens holding barrel in an assembling process, a lens barrel and an optical device including the same are provided. The lens barrel includes: a first barrel including: a first cylinder that includes a lens and is cylindrical, and a first flange formed around an outer surface of the first cylinder; and a second barrel including: a second cylinder that is cylindrical and aligned with respect to the first cylinder, a second flange that is formed on an inner surface of the second cylinder and supports one surface of the first flange, and a plurality of supports that protrude from the inner surface of the second cylinder in a direction parallel to a surface of the second flange and support another surface of the first flange. | 09-09-2010 |
20100226024 | BARREL MODULE AND IMAGING APPARATUS INCLUDING THE SAME - A barrel module and an imaging apparatus including the same. The barrel module includes: a base having a surface on which an image pickup device is disposed; a lens barrel disposed on the base; a driver for providing driving power to move the lens barrel up and down over the base; a clip connected to the driver to be disposed between the driver and the lens barrel; and an elastic member for providing elasticity between the lens barrel and the clip, wherein the lens barrel moves from an original position toward the base according to an external force is applied, and when the external force is removed, the lens barrel goes back to the original location due to the elasticity of the elastic member. | 09-09-2010 |
Patent application number | Description | Published |
20090034348 | WRITE DRIVER CIRCUIT OF AN UNMUXED BIT LINE SCHEME - A write driver circuit of a semiconductor memory to provide an unmuxed bit line scheme which reduces a height of an unmuxed Y-path so as to reduce an area of a chip in the memory. The write driver circuit can include an input latch circuit which latches input data, in response to an input enable signal; a first write driver which receives write data output from the input latch circuit, in response to a write enable signal, and outputs data to a bit line; and a second write driver which receives inverse data of the write data output from the input latch circuit, in response to the write enable signal, and outputs data to a complementary bit line, wherein the first and second write drivers have a NAND gate type structure and function as a write driver and a precharge driver. | 02-05-2009 |
20100177106 | ARBITRATION CIRCUIT TO ARBITRATE CONFLICT BETWEEN READ/WRITE COMMAND AND SCAN COMMAND AND DISPLAY DRIVER INTEGRATED CIRCUIT HAVING THE SAME - An arbitration circuit to arbitrate an issue between a read/write command and a scan command and a display driver integrated circuit including the arbitration circuit. The arbitration circuit includes a latch unit having a first latch circuit that latches and outputs a first signal related to a scan command and a second latch circuit that latches and outputs a second signal related to a read/write command, wherein the latch unit resets outputs of the first latch circuit and/or the second latch circuit in response to a ready signal related to a memory operation, and a maintaining unit to receive outputs of the first latch circuit and the second latch circuit, to generate a first internal signal to activate a scanning operation and a second internal signal to activate a reading/writing operation, maintain the first internal signal and the second internal signal, and to selectively activate the first internal signal or the second internal signal by changing the state of at least one of the first internal signal and second internal signal in response to the reset operation. | 07-15-2010 |
20120206988 | NEGATIVE VOLTAGE GENERATOR AND SEMICONDUCTOR MEMORY DEVICE - A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair. | 08-16-2012 |
20150234977 | METHOD OF VERIFYING LAYOUT OF MASK ROM - A method of verifying a layout of a mask read only memory (ROM) includes: receiving source ROM code, bitmap data, and layout design data of the mask ROM; generating coordinate data of a bit determining unit based on the layout design data; and determining an error cell based on the coordinate data of the bit determining unit, the bitmap data, and the source ROM code. | 08-20-2015 |
20160003901 | SCAN CHAIN CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A scan chain circuit includes first through N-th flip-flops connected in series to sequentially transfer data in response to a control signal, where N is an integer greater than 1. In the first through N-th flip-flops, the data are transferred in a first direction from the first flip-flop to the N-th flip-flop. The control signal is applied to the first through N-th flip-flops in a second direction opposite to the first direction from the N-th flip-flop to the first flip-flop. | 01-07-2016 |
Patent application number | Description | Published |
20100002531 | Multi-Port Memory Devices Having Clipping Circuits Therein that Inhibit Data Errors During Overlapping Write and Read Operations - An integrated circuit device includes a memory array having a multi-port memory cell (e.g., dual-port SRAM cell) therein. This multi-port memory cell includes at least first and second read/write ports, which may be provided by respective access transistors (e.g., N-type MOS transistors) that are responsive to word line signals. The first and second read/write ports are electrically coupled to the first and second bit lines, respectively. A first clipping circuit is also provided. The first clipping circuit is responsive to a first write control signal. The first clipping circuit is configured to bias the first bit line with a read blocking voltage during a first “overlapping” operation to write data from the second bit line into the multi-port memory cell concurrently with reading data from the multi-port memory cell onto the first bit line. | 01-07-2010 |
20110306762 | ACID ADDITION SALT OF UDENAFIL, PREPARATION METHOD THEREOF AND PHARMACEUTICAL COMPOSITION COMPRISING THE SAME - The present invention provides an acid addition salt of Udenafil, a preparation method thereof and a pharmaceutical composition comprising the same. The acid addition salt of Udenafil in which Udenafil is bonded to an organic acid selected from the group consisting of oxalic acid, benzenesulfonic acid, camphorsulfonic acid, cinnamic acid, adipic acid and cyclamic acid, has excellent solubility in an aqueous medium, water stability and crystallinity, thereby being suitably applied for a pharmaceutical composition. | 12-15-2011 |
20150379098 | METHOD AND APPARATUS FOR MANAGING DATA - A method is provided for managing data in an electronic device, the method including: detecting a request for tagging a data record; selecting a portion of the data record in response to the request; identifying a content item based on the selected portion of the data record; and associating the content item with the data record. | 12-31-2015 |
Patent application number | Description | Published |
20120206820 | ZOOM LENS BARREL ASSEMBLY - A zoom lens barrel assembly including: a first zoom ring comprising a first protrusion; a guide ring disposed around the first zoom ring comprising a first guide slot through which the first protrusion passes, and a second guide slot; a second zoom ring comprising a second protrusion, and movable in an axial direction; a first cylinder comprising a guide groove into which the second protrusion inserts, and a third protrusion passing through the second guide slot, and disposed between the first and second zoom rings; a second cylinder disposed around the guide ring comprising a fourth protrusion, a first groove portion into which the first protrusion inserts, and a second groove portion into which the third protrusion inserts, and supporting the first zoom ring and the first cylinder; and an external cylinder disposed around the second cylinder and comprising a third groove portion into which the fourth protrusion inserts. | 08-16-2012 |
20120206821 | ZOOM LENS BARREL ASSEMBLY - A zoom lens barrel assembly includes: a zoom ring having a cylindrical shape, and comprising an inlet portion formed in a boundary of one end thereof and a first protrusion; a guide ring disposed around the zoom ring, and comprising a first guide hole through which the first protrusion passes, and movably supporting the zoom ring in an axial direction, and a second guide hole; and a cylinder disposed in the zoom ring, for moving and rotating between a position where the cylinder is accommodated in the zoom ring and a position where the cylinder moves away from the zoom ring in the axial direction, and comprising a second protrusion that passes through the second guide hole, accommodated in the inlet portion at the position where the cylinder is accommodated, and pressing one end of the inlet portion when the cylinder moves away from the zoom ring. | 08-16-2012 |
20130335832 | ZOOM LENS BARREL ASSEMBLY - A zoom lens barrel assembly includes: a first zoom ring comprising a first protrusion; a guide ring disposed around the first zoom ring comprising a first guide slot through which the first protrusion passes, and a second guide slot; a second zoom ring comprising a second protrusion, and movable in an axial direction; a first cylinder comprising a guide groove into which the second protrusion inserts, and a third protrusion passing through the second guide slot, and disposed between the first and second zoom rings; a second cylinder disposed around the guide ring comprising a fourth protrusion, a first groove portion into which the first protrusion inserts, and a second groove portion into which the third protrusion inserts, and supporting the first zoom ring and the first cylinder; and an external cylinder disposed around the second cylinder and comprising a third groove portion into which the fourth protrusion inserts. | 12-19-2013 |
Patent application number | Description | Published |
20130028261 | SYSTEM-ON-CHIP-BASED NETWORK PROTOCOL IN CONSIDERATION OF NETWORK EFFICIENCY - An SoC-based system network protocol in consideration of network efficiency is disclosed. An MSB of a command signal containing an instruction defining information that is contained in a transfer signal transferred from an initiator to a destination via a channel or in a response signal transferred from the destination via the channel indicates that a highest priority is assigned to a transaction between the initiator and the destination in the network, when the instruction contained in the command signal corresponds to address information contained in the transfer signal and response information contained in the response signal, and indicates last data of a signal transferred between the initiator and the destination when the instruction contained in the command signal corresponds to control information contained in the transfer signal and data contained in the transfer signal and the response signal. | 01-31-2013 |
20130151795 | APPARATUS AND METHOD FOR CONTROLLING MEMORY - Disclosed herein are an apparatus and method for controlling memory. The apparatus includes a memory access request buffer unit, a memory access request control unit, and a bank control unit. The memory access request buffer unit determines and stores memory access request order so that the plurality of memory access requests is processed in the order of input except that memory access requests attempting to access the same bank and the same row are successively processed. The memory access request control unit reads the memory access requests from the memory access request buffer unit in the determined order, distributes the memory access requests to banks, and transfers the memory access requests to memory. The bank control unit stores a preset number of memory access requests in each of buffer units for respective banks, and controls the operating state of each of the banks. | 06-13-2013 |
20130185525 | SEMICONDUCTOR CHIP AND METHOD OF CONTROLLING MEMORY - Disclosed herein are a semiconductor chip for adaptively processing a plurality of commands to request memory access, and a method of controlling memory. The semiconductor chip includes a storage unit ad a control unit. The storage unit stores a memory access request to be currently processed and a plurality of memory access requests received before the memory access request to be currently processed in received order. The control unit processes the memory access request to be currently processed and the plurality of memory access requests received before the memory access request to be currently processed, which have been stored in the storage unit, in received order, except that memory access requests attempting to access the same bank and the same row are successively processed. | 07-18-2013 |
20130286762 | MEMORY CONTROL APPARATUS AND METHOD - Provided are a memory control apparatus and a memory control method. In the memory control apparatus and memory control method, data are distributively stored in a plurality of banks in sequence, and the corresponding data are written to or read from the memory, based on row address information obtained by exchanging a portion of row information and bank information with each other. According to the invention, if a new row begins when the host or the processor accesses the memory, a host or a processor accesses another bank, and thus the block data can be read or written without a waiting cycle. In addition, the memory control apparatus and the memory control method can be implemented with low complexity available through simple address conversion in the memory control apparatus. | 10-31-2013 |