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| 20090013303 | METHOD OF CREATING MASK LAYOUT IMAGE AND IMAGING SYSTEM - Provided are a method of creating a mask layout image from a target image, a computer readable storage medium having stored thereon a computer program for executing the method, and an imaging system. The method includes reading all or a part of a target image to be transcribed on a substrate; defining a mask data set including a plurality of pixels having a predetermined transmittance characteristic; defining a weighting function having a non-zero value within a critical range; defining a convolution kernel determined by an illumination meter; and creating the mask layout image that minimizes an image fitting function by using the weighting function and the convolution kernel. | 01-08-2009 |
| 20100112466 | OPTICAL MASKS AND METHODS FOR MEASURING ABERRATION OF A BEAM - An optical mask for use with an exposure beam includes a mask substrate adapted to be placed on a traveling path of the exposure beam. A reference pattern is formed on the mask substrate. The reference pattern is adapted to direct the exposure beam to travel in a predetermined reference direction. A comparative pattern is formed on the mask substrate. The comparative pattern is adapted to direct the exposure beam to travel in a direction inclined at a predetermined angle with respect to the reference direction. | 05-06-2010 |
| 20110207247 | METHOD OF CORRECTING OVERLAY AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING THE SAME - A method of correcting an overlay includes setting a reference map having information relating to predetermined positions of a substrate. An overlay value is measured at each of the predetermined positions to obtain a plurality of overlay measurement values. The plurality of overlay measurement values is applied to a polar coordinate function to calculate a correlation coefficient of the polar coordinate function. The polar coordinate function uses coordinate values of the predetermined positions as parameters. | 08-25-2011 |
| 20110227070 | GETTERING MEMBERS, METHODS OF FORMING THE SAME, AND METHODS OF PERFORMING IMMERSION LITHOGRAPHY USING THE SAME - Provided herein are gettering members that include a monitor substrate and a conditioning layer thereon. Also provided herein are methods of forming gettering layers and methods of performing immersion lithography processes using the same. | 09-22-2011 |
| 20110317163 | Method of Aligning a Wafer and Method of Monitoring a Lithography Process Including the Same - A method of aligning a wafer includes irradiating light onto a plurality of alignment marks of a wafer, detecting signals outputted from the alignment marks to obtain alignment position offsets, selecting a set of the alignment marks corresponding to the alignment position offsets having a same or similar distribution, and aligning the wafer based the selected alignment marks. | 12-29-2011 |
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| 20100015813 | GAP PROCESSING - Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations. | 01-21-2010 |
| 20110312171 | Methods Of Forming Integrated Circuitry Comprising Charge Storage Transistors - Methods include forming a charge storage transistor gate stack over semiconductive material. One such stack includes a tunnel dielectric, charge storage material over the tunnel dielectric, a high-k dielectric over the charge storage material, and conductive control gate material over the high-k dielectric. The stack is etched at least to the tunnel dielectric to form a plurality of charge storage transistor gate lines over the semiconductive material. Individual of the gate lines have laterally projecting feet which include the high-k dielectric. After etching the stack to form the gate lines, ions are implanted into an implant region which includes the high-k dielectric of the laterally projecting feet. The ions are chemically inert to the high-k dielectric. The ion implanted high-k dielectric of the projecting feet is etched selectively relative to portions of the high-k dielectric outside of the implant region. | 12-22-2011 |
| 20120040534 | GAP PROCESSING - Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations. | 02-16-2012 |
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| 20110085385 | Nonvolatile Memory Devices Having Dummy Cell and Bias Methods Thereof - Provided are nonvolatile memory devices and methods of operating thereof. The nonvolatile memory devices include: dummy cells connected to a dummy bit line; and a dummy bit line bias circuit providing a dummy bit line voltage to the dummy bit line during a program operation, wherein, due to the dummy bit line voltage, at least one of the dummy cells is programmed with a threshold voltage lower than the top programmed state and higher than an erased state during the program operation. | 04-14-2011 |
| 20110286274 | NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - A nonvolatile memory device preventing a program disturb, a program method thereof and a memory system including the nonvolatile memory device and the program method. The nonvolatile memory device includes a memory cell array; first and second word lines connected to a NAND string in the memory cell array; a third word line connected to the NAND string, the third word line being disposed between the first and second word lines; a temperature sensor configured to measure the temperature of the nonvolatile memory device; and a voltage generator configured to generate first and second pass voltages and a program voltage, and the voltage level of at least one of the first and second pass voltages is controlled according to the measured temperature. When a program operation is performed, the program voltage is applied to the third word line, the first pass voltage is applied to the first word line, the second pass voltage is applied to the second word line. | 11-24-2011 |
| 20110305079 | NONVOLATILE MEMORY DEVICE INCLUDING DUMMY MEMORY CELL AND PROGRAM METHOD THEREOF - A nonvolatile memory device including a dummy memory cell and a method of programming the same, wherein the nonvolatile memory device includes a dummy memory cell, and a plurality of memory cells serially connected to the dummy memory cell. The nonvolatile memory device sets a voltage provided to the dummy memory cell according to a distance between a selected memory cell among the plurality of memory cells and the dummy memory cell when a program operation is performed. | 12-15-2011 |
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| 20080211945 | Image sensor with extended dynamic range - An image sensor includes a first sub-pixel, a second sub-pixel, and an image processor. The first sub-pixel generates a first image signal with a first sensitivity, and the second sub-pixel generates a second image signal with a second sensitivity less than the first sensitivity. The image signal processor adds a change in the second image signal from a saturation level to the first image signal to generate a final image signal when the first sub-pixel is saturated. | 09-04-2008 |
| 20100062559 | Methods of manufacturing image sensors having shielding members - An epitaxial layer may be formed on a substrate having a first region and a second region. A photo diode may be formed on a first portion of the epitaxial layer in the first region of the substrate. At least one transfer transistor may be formed on the epitaxial layer adjacent to the photo diode. A plurality of transistors may be formed on a second portion of the epitaxial layer in the second region. An insulation layer may be formed to cover the photo diode, the at least one transfer transistor and the plurality of transistors. A plurality of connections may be formed through the insulation layer to be electrically connected with the at least one transfer transistor and the plurality of transistors in the second region. A shielding member may be formed to expose the photo diode. The epitaxial layer and/or the substrate may be treated with a hydrogen plasma before forming the shielding member to remove dangling bonds of silicon-oxygen and/or silicon-silicon. | 03-11-2010 |
| 20110163362 | Methods of fabricating image sensors and image sensors fabricated thereby - A method of fabricating an image sensor may include providing a substrate including light-receiving and non-light-receiving regions; forming a plurality of gates on the non-light-receiving region; ion-implanting a first-conductivity-type dopant into the light-receiving region to form a first dopant region of a pinned photodiode; primarily ion-implanting a second-conductivity-type dopant, different from the first-conductivity-type dopant, into an entire surface of the substrate, using the gates as a first mask; forming spacers on both side walls of the gates; and secondarily ion-implanting the second-conductivity-type dopant into the entire surface of the substrate, using the plurality of gates including the spacers as a second mask, to complete a second dopant region of the pinned photodiode. An image sensor may include the substrate; a transfer gate formed on the non-light-receiving region; a first dopant region in the light-receiving region; and a second dopant region formed on a surface of the light-receiving region. | 07-07-2011 |
| 20110204468 | Image sensor and method of manufacturing the same - Example embodiments disclose an image sensor capable of preventing or reducing image lag and a method of manufacturing the same. Example methods may include forming a gate insulating film and a gate conductive film doped with a first-conductive-type dopant on a semiconductor substrate; forming a transfer gate pattern by patterning the gate insulating film and the gate conductive film; and fabricating a transfer gate electrode by forming a first-conductive-type photodiode in the semiconductor substrate adjacent to one region of the transfer gate pattern, by forming a second-conductive-type photodiode on the first-conductive-type photodiode, and by forming a first-conductive-type floating diffusion region in the semiconductor substrate adjacent to the other region of the transfer gate pattern. | 08-25-2011 |
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| 20090105973 | Noncontact Measurement Method of Currents on Superconductive Wires Connected in Parallel - A noncontact method for measuring currents flowing through superconductive wires connected in parallel is provided. The method includes arranging hall sensors for measuring voltage levels based on magnetic fields generated around the superconductive wires, setting a matrix relation between the measured voltage values, values of currents flowing through the superconductive wires, and a variable matrix having variables defining relations between the voltage values and the current values, applying predetermined current levels to the superconductive wires a number of times and measuring voltage values through the hall sensors, substituting the predetermined current values and the measured voltage values into the matrix relation to calculate the variables of the variable matrix, and substituting the calculated variable matrix and unknown voltage values, measured by the hall sensors when unknown currents flow through the superconductive wires, into the matrix relation to calculate values of the unknown currents flowing through the superconductive wires. | 04-23-2009 |
| 20110218110 | SUPERCONDUCTING POWER TRANSFORMING APPARATUS - The present invention relates to a superconducting power transforming apparatus. The superconducting power transforming apparatus according to the present invention comprises a transformer housing having a transforming cable passing hole and filled with a liquid cooling means; a superconducting transformer housed in the transformer housing in a state that the superconducting transformer is immersed in the liquid cooling means; a tap changer housing having a tap changing cable passing hole and vacuum-sealed from outside; a power tap changer housed in the vacuum tap changer housing; and a cable linking pipe vacuum-sealed from the transformer housing and the tap changer housing, and linking the transforming cable passing hole with the tap changing passing hole in order that a transformer winding tap cable connecting the superconducting transformer and the power tap changer passes through. Consequently, it is possible to guarantee stable operation of a superconducting transformer which works at an extremely low temperature and a power tap changer as like On-Load Tap Changer which works at low temperature. | 09-08-2011 |
| 20110239443 | MULTIPLE TRANSPOSITION METHOD FOR SUPERCONDUCTING WIRE - Provided is a multiple transposition method for superconducting wire, by making each superconducting wire unit from second-generation superconducting wires that were firstly transposed and then transposing each superconducting wire unit in such a manner that the phase of each unit can be changed along the length, comprising preparing wires by making curves on superconducting wires in such a manner that the superconducting wires of a thin multiple layer grown epitaxially are slit in zigzags and then making the curves repeatedly and by machining the wires with a desired length; making first-transposed superconducting wire units by combining a plurality of the prepared wires such that curves of adjacent wires come in touch to each other and are superposed; preparing a superconducting wire unit bundle by arranging the first-transposed superconducting wires units and by locating a plurality of the first-transposed superconducting wire units in parallel along the length; and making a second transposition on the first-transposed superconducting wire units by rotating the plurality of superconducting wire units on the central axis of the superconducting wire unit bundle along the length to be twisted and combined with each other. | 10-06-2011 |
| 20110270557 | MEASURING METHOD OF CRITICAL CURRENT DENSITY OF SUPERCONDUCTOR WIRES USING MEASUREMENT OF MAGNETIZATION LOSS - A method for measuring critical current density of superconductor wires according to the present invention is characterized in that it includes: (a) applying an external magnetic field to the superconductor wires, (b) measuring a magnetization loss of the superconductor wires according to the application of the external magnetic field, (c) normalizing the measured magnetization loss, and then calculating a fully-penetration magnetic field of the superconductor wires according to the normalized magnetization loss, (d) calculating a critical current density of the superconductor wires according to the calculated fully-penetration magnetic field. Therefore, the critical current density of parallel superconductor wires such as stacked superconductor wires may be measured without applying current to the superconductor wires directly. | 11-03-2011 |
| 20120068389 | Methods of fabricating polycrystalline ceramic for thermoelectric devices - Provided is a method of fabricating polycrystalline ceramic for thermoelectric devices. The method includes preparing calcined ceramic powders, forming a ceramic sheet by uni-axially pressing the calcined ceramic powders, stacking a plurality of the ceramic sheets in a uni-axial direction, and cofiring the stacked the plurality of the ceramic sheets. | 03-22-2012 |
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| 20100079176 | Inverter Driver And Load Driver Including The Same, And Driving Method Thereof - A load driver includes an inverter and an inverter driver. The inverter converts an input voltage into a driving voltage of a discharge lamp using at least one first switch for switching according to a duty ratio, and the inverter driver controls the inverter. The inverter driver controls the duty ratio using a voltage of a capacitor and a control signal having a waveform that is repeated with a predetermined frequency. The capacitor is charged and discharged by a current corresponding to a difference between a feedback voltage corresponding to a current flow to the discharge lamp and a reference voltage. Such inverter driver controls to gradually increase the output voltage of the inverter in the soft start period by setting the voltage of the capacitor as a voltage corresponding to the control signal. | 04-01-2010 |
| 20100327758 | LED Light Emitting Device And Driving Method Thereof - The present invention relates to an LED light emitting device and a driving method, and discloses a technology that may improve a slew rate of a channel current flowing through an LED channel when driving with a pulse width modulation method. For this, the present invention includes an LED channel consisting of a plurality of LED elements that are consecutively and serially connected, a current control switch that is connected to the end of the LED channel and performs a switching operation, and an operational amplifier that controls the switching operation of the current control switch according to a pulse width modulation signal. The LED driver samples an output voltage at the operational amplifier when the pulse width modulation signal is in an on state, and maintains the output voltage of the operational amplifier when the pulse width modulation signal is in an off state. | 12-30-2010 |
| 20120126703 | DRIVING APPARATUS AND DRIVING METHOD OF LED DEVICE - A driving apparatus of an LED device is provided. The LED device includes a plurality of LED channels, and each LED channel includes a plurality of LEDs connected in series. A power converter has an output terminal connected to a first terminal of each LED channel, and converts an input voltage into an output voltage to output the output voltage to the output terminal. A plurality of current controllers correspond to the plurality of LED channels, respectively. Each current controller is connected to a second terminal of a corresponding LED channel, and controls a current of the corresponding LED channel. The voltage sensor outputs a sensed voltage corresponding to the output voltage of the output terminal. The fault controller determines whether to stop operation of the power converter by comparing the sensed voltage with a reference voltage. | 05-24-2012 |
