Patent application number | Description | Published |
20080246099 | LOW TEMPERATURE POLY OXIDE PROCESSES FOR HIGH-K/METAL GATE FLOW - An integrated circuit device is disclosed as comprising a feature that is susceptible to oxidation. A poly-oxide coating is used over the feature susceptible to oxidation to protect the feature susceptible to oxidation from oxidizing. Various method can be used to form the poly-oxide coating include conversion of a ploy-silicon coating using UV O | 10-09-2008 |
20090053883 | METHOD OF SETTING A WORK FUNCTION OF A FULLY SILICIDED SEMICONDUCTOR DEVICE, AND RELATED DEVICE - A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction. | 02-26-2009 |
20090170346 | LOW TEMPERATURE POLYSILICON OXIDE PROCESS FOR HIGH-K DIELECTRIC/METAL GATE STACK - A method for preventing oxidation in a high-k dielectric/metal gate stack in the manufacture of an integrated circuit device is disclosed. In a detailed embodiment, a PMOS region stack has nitrided hafnium silicide, tungsten, tantalum nitride and polysilicon layers. An NMOS region stack has nitrided hafnium silicide, tungsten silicide, tantalum nitride and polysilicon layers. A thin polysilicon layer deposited over the stacks is converted to an oxide using a low temperature ultraviolet ozone oxidation process or a plasma nitridation using decoupled plasma nitridation or NH | 07-02-2009 |
20100155860 | TWO STEP METHOD TO CREATE A GATE ELECTRODE USING A PHYSICAL VAPOR DEPOSITED LAYER AND A CHEMICAL VAPOR DEPOSITED LAYER - One embodiment of the present invention relates a semiconductor device formed by utilizing a two step deposition method for forming a gate electrode without causing damages to an underlying gate dielectric material. In one embodiment, a first layer of gate electrode material (first gate electrode layer) is formed onto the surface of a gate dielectric material using a deposition that does not damage the gate dielectric material (e.g., physical vapor deposition) thereby resulting in a damage free interface between the gate dielectric material and the gate electrode material. A second layer of gate electrode material (second gate electrode layer) is then formed onto the first layer of gate electrode material using a chemical deposition method that provides increased deposition control (e.g., good layer uniformity, impurity control, etc.). The first and second gate electrode layers are then selectively patterned to cumulatively form a semiconductor device's gate electrode. | 06-24-2010 |
20100164008 | METHOD FOR INTEGRATION OF REPLACEMENT GATE IN CMOS FLOW - Semiconductor devices and fabrication methods are provided, in which metal transistor replacement gates are provided for CMOS transistors. The process provides dual or differentiated work function capability (e.g., for PMOS and NMOS transistors) in CMOS processes. | 07-01-2010 |
20100187613 | Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device - A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction. | 07-29-2010 |
20110111586 | Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device - A method of setting a work function of a fully silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a silicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the silicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction. | 05-12-2011 |
20120231590 | Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device - A method of setting a work function of a filly silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a suicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the suicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction. | 09-13-2012 |
Patent application number | Description | Published |
20080268599 | STRUCTURE AND METHOD FOR A TRIPLE-GATE TRANSISTOR WITH REVERSE STI - Exemplary embodiments provide triple-gate semiconductor devices isolated by reverse STI structures and methodologies for their manufacture. In an exemplary process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The exemplary triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality. | 10-30-2008 |
20090068828 | DUAL WORK FUNCTION CMOS DEVICES UTILIZING CARBIDE BASED ELECTRODES - Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region. | 03-12-2009 |
20100078738 | Method to Maximize Nitrogen Concentration at the Top Surface of Gate Dielectrics - An integrated circuit having a gate dielectric layer ( | 04-01-2010 |
20100127335 | Methods to Enhance Effective Work Function of Mid-Gap Metal by Incorporating Oxygen and Hydrogen at a Low Thermal Budget - A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed. | 05-27-2010 |
20100127336 | STRUCTURE AND METHOD FOR METAL GATE STACK OXYGEN CONCENTRATION CONTROL USING AN OXYGEN DIFFUSION BARRIER LAYER AND A SACRIFICIAL OXYGEN GETTERING LAYER - A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed. | 05-27-2010 |
20100167517 | CROSS-CONTAMINATION CONTROL FOR PROCESSING OF CIRCUITS COMPRISING MOS DEVICES THAT INCLUDE METAL COMPRISING HIGH-K DIELECTRICS - A cross method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface, wherein the bevel semiconductor surface and backside semiconductor surface include silicon or germanium. A metal including high-k gate dielectric layer is formed on at least the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and backside semiconductor surface. The high-k dielectric material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed while protecting the high-k dielectric layer on the topside semiconductor surface. The selective removing includes a first oxidizing treatment, and a fluoride including wet etch follows the first oxidizing treatment. The fabrication of the IC is completed including forming at least one metal gate layer on the high-k gate dielectric layer after the selectively removing step. | 07-01-2010 |
20100323486 | TRIPLE-GATE TRANSISTOR WITH REVERSE SHALLOW TRENCH ISOLATION - Example embodiments provide triple-gate semiconductor devices isolated by reverse shallow trench isolation (STI) structures and methods for their manufacture. In an example process, stacked layers including a form layer over a dielectric layer can be formed over a semiconductor substrate. One or more trenches can be formed by etching through the stacked layers. The one or more trenches can be filled by an active area material to form one or more active areas, which can be isolated by remaining portions of the dielectric layer. Bodies of the active area material can be exposed by removing the form layer. One or more triple-gate devices can then be formed on the exposed active area material. The example triple-gate semiconductor devices can control the dimensions for the active areas and provide less isolation spacing between the active areas, which optimizes manufacturing efficiency and device integration quality. | 12-23-2010 |
20110204454 | SEMICONDUCTOR DEVICE INCLUDING SION GATE DIELECTRIC WITH PORTIONS HAVING DIFFERENT NITROGEN CONCENTRATIONS - An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of <2 atomic %, (ii) a bulk portion having an average N concentration >10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is ≧2 atomic % less than a peak N concentration of the bulk portion. | 08-25-2011 |
20110207314 | Methods to Enhance Effective Work Function of Mid-Gap Metal by Incorporating Oxygen and Hydrogen at a Low Thermal Budget - A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed. | 08-25-2011 |
20120032280 | MOS TRANSISTORS INCLUDING SiON GATE DIELECTRIC WITH ENHANCED NITROGEN CONCENTRATION AT ITS SIDEWALLS - A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack. | 02-09-2012 |
20130221451 | MOS TRANSISTORS INCLUDING SiON GATE DIELECTRIC WITH ENHANCED NITROGEN CONCENTRATION AT ITS SIDEWALLS - A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack. | 08-29-2013 |
20130228879 | SEMICONDUCTOR DEVICE INCLUDING SION GATE DIELECTRIC WITH PORTIONS HAVING DIFFERENT NITROGEN CONCENTRATIONS - An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of <2 atomic %, (ii) a bulk portion having an average N concentration >10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is ≧2 atomic % less than a peak N concentration of the bulk portion. | 09-05-2013 |
20130337656 | STRUCTURE AND METHOD FOR DUAL WORK FUNCTION METAL GATE CMOS WITH SELECTIVE CAPPING - A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a mid gap metal with a high work function/low oxygen affinity cap and method of forming. | 12-19-2013 |
20140120668 | STRUCTURE AND METHOD FOR METAL GATE STACK OXYGEN CONCENTRATION CONTROL USING AN OXYGEN DIFFUSION BARRIER LAYER AND A SACRIFICIAL OXYGEN GETTERING LAYER - A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed. | 05-01-2014 |
20140183653 | HIGH-K METAL GATE - An integrated circuit containing metal replacement gates may be formed by forming a nitrogen-rich titanium-based barrier between a high-k gate dielectric layer and a metal work function layer of a PMOS transistor. The nitrogen-rich titanium-based barrier is less than 1 nanometer thick and has an atomic ratio of titanium to nitrogen of less than 43:57. The nitrogen-rich titanium-based barrier may be formed by forming a titanium based layer over the gate dielectric layer and subsequently adding nitrogen to the titanium based layer. The metal work function layer is formed over the nitrogen-rich titanium-based barrier. | 07-03-2014 |
20150311126 | STRUCTURE AND METHOD FOR METAL GATE STACK OXYGEN CONCENTRATION CONTROL USING AN OXYGEN DIFFUSION BARRIER LAYER AND A SACRIFICIAL OXYGEN GETTERING LAYER - A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed. | 10-29-2015 |
Patent application number | Description | Published |
20140262326 | PURGING FLUID CIRCUITS IN WELLBORE CONTROL DEVICES - The disclosure relates to purging a RCD including a bearing of contaminants with a fluid circuit, the fluid circuit having at least one housing adjacent to the RCD, a first plurality of valves within the bearing, a second plurality of valves within the housing, at least one inlet port located on the RCD, each inlet port being connected to the housing, at least one outlet port located on the RCD, each outlet port being connected to the housing, and a purge outlet in fluid communication with the fluid circuit. | 09-18-2014 |
20150096766 | FLOATING DEVICE RUNNING TOOL - A running tool and delivery and/or retrieving apparatus, and method for use, are designed for optionally delivering and optionally retrieving an oilfield device down a borehole. A kelly extends into the borehole. The tool has a journal configured for slidable movement along the kelly, an engagement disk mounted around the journal configured for engaging the device, and a plurality of fins attached perpendicular to an outer circumference of the journal. The proximal fins extend radially from the outer circumference of the journal toward the engagement disk, are butted against the engagement disk and extend to a diameter complementary to an outer diameter of the engagement disk. The plurality of proximal fins surround and are arranged concentric with the journal. | 04-09-2015 |
20150226025 | POSITIVE RETRACTION LATCH LOCKING DOG FOR A ROTATING CONTROL DEVICE - A latch and method for use is provided for latching an item of oilfield equipment. The latch has a housing containing a latch member, and the latch member is movable between a radially engaged position in which it is engaged with the item of oilfield equipment, and a radially retracted position in which it is disengaged from the item of oilfield equipment. An actuator is configured to drive the latch member into the radially engaged position. Further, the actuator is configured to drive the latch member toward the radially retracted position. | 08-13-2015 |
20150315845 | SEALING ELEMENT MOUNTING - A sealing assembly for sealing against a piece of oilfield equipment in a wellbore. The sealing assembly has a support housing and the support housing defines an inner wall and a port configured for fluid communication with the wellbore. Such inner wall defines a stop shoulder, and the support housing has a limit structure proximate one or both end(s). A sealing element is contained within the support housing. A ring is connected to the sealing element at one or both end(s). Each ring is configured for slidable movement along the inner wall of the support housing and further configured to float between the stop shoulder and the limit structure. | 11-05-2015 |
20150315874 | BEARING ASSEMBLY COOLING METHODS - The disclosure relates to apparatus and methods for cooling a RCD at a wellbore including a bearing assembly configured for operating in the RCD. A fixed latch with a heat exchanger system and a volume of a cooling medium is configured for reducing heat proximate the bearing assembly, an inner member, and one or more seals between the bearing assembly and the inner member. | 11-05-2015 |