| Patent application number | Description | Published |
|---|
| 20090089407 | Deployment Wizard - A method and apparatus are provided for collecting deployment information from a user for a multi-tier computer system. The method includes the steps of receiving a deployment size of the multi-tier system from the user and identifying a set of virtual appliances by function based upon the deployment size received from the user. The method further includes the steps of prompting the user for a name for each identified virtual appliance, collecting network information of each virtual appliance based upon the name and generating a deployment configuration file for a mandatory virtual appliance of the set of virtual appliances. | 04-02-2009 |
| 20100011353 | IMAGE INSTALLER - A method, apparatus, and software are provided for deploying at least one virtual appliance to a deployment site of a multi-tier computer system. The method includes reading a deployment configuration file to identify at least one virtual appliance to deploy, transferring the identified at least one virtual appliance to the computer system, registering the at least one virtual appliance with a virtualization software of the computer system, changing the network settings of the virtualization software to match the deployment configuration file, placing a copy of the deployment configuration file on the virtualization software, and the virtualization software installing the identified at least one virtual appliance on the computer system. | 01-14-2010 |
| 20100235482 | Virtual Appliance Automation Tool - A method and apparatus are provided for creating a virtual machine installer for use in a multi-tier computer system. The method includes the steps of providing a plurality of interactive applications operating together to achieve a predetermined enterprise objective, providing a plurality of substantially identical virtual appliances, modifying the plurality of virtual appliances by installing a respective interactive application into each of the plurality of virtual appliances (VAs), generating a catalog of the modified virtual appliances, and saving the modified virtual appliances and the catalog on a medium. | 09-16-2010 |
| Patent application number | Description | Published |
|---|
| 20090187372 | SIN-COS SENSOR ARRANGEMENT, INTEGRATED CIRCUIT AND METHOD THEREFOR - A Sin-Cos sensor arrangement comprises a Sin-Cos sensor operably coupled to signal processing logic via a hardware interface. The hardware interface is arranged to provide the signal processing logic with analogue sine and cosine waveforms indicative of fine position data and binary counterparts of the analogue sine and cosine waveforms (Phase_A and Phase_B indicative of rough position data. The signal processing logic is arranged to determine a position and speed of the Sin-Cos sensor by compensating for inaccuracies between analogue sine and cosine waveforms and their binary counterparts. In this manner, a fully software-based solution provides a fast, efficient and high accuracy position and speed estimation based on the processing of the analogue sine and cosine signals and the digital representation thereof of the Sin-Cos sensor. | 07-23-2009 |
| 20100169696 | PROCESSOR SYSTEM EMPLOYING A SIGNAL ACQUISITION MANAGING DEVICE AND SIGNAL ACQUISITION MANAGING DEVICE - A processor system having a processor core configured to control an external apparatus in accordance with a control algorithm; a signal acquisition managing device configured to receive state signals provided by the apparatus, perform corresponding actions, and generate corresponding synchronized command signals; and a peripheral module structured to receive the synchronized command signals and generate output signals to be processed by the processor core in accordance with the control algorithm. | 07-01-2010 |
| 20100213964 | TIMER UNIT, SYSTEM, COMPUTER PROGRAM PRODUCT AND METHOD FOR TESTING A LOGIC CIRCUIT - A timer unit includes a timer for timing the period of time the logic circuit has been in the self-test mode. A comparator is connected to the timer, for comparing the period of time with a maximum for the period of time the logic circuit is allowed to be in the self-test mode and outputting an error signal when the period of time exceeds the maximum. The test timer unit further includes a mode detector for detecting a switching of the logic circuit to the self-test mode. The mode detector is connected to the timer, for starting the timer upon the switching to the self-test mode and stopping the timer upon a switching of the logic circuit out of the self-test mode. The timer unit can be used in a system for testing a logic circuit which includes a test routine module containing a set of instructions which forms a test routine for performing a test on a tested part of the logic circuit. The system has a mode control unit containing a set of instructions which is executable by the logic circuit, for switching the logic circuit from and to a test mode in which a part of the logic circuit can be subjected to a selected test by executing a selected test routine. | 08-26-2010 |
