| Patent application number | Description | Published |
|---|
| 20080226001 | ADJACENT CHANNEL INTERFERENCE DETECTION FOR WIRELESS COMMUNICATION - Techniques for detecting adjacent channel interference (ACI) in a wireless communication system are described. Input inphase (I) and quadrature (Q) samples are filtered with a first filter response to obtain filtered I and Q samples. The first filter response is designed to pass signal in an adjacent frequency channel while suppressing signals in a desired frequency channel and non-adjacent frequency channels. Correlations of the filtered I and Q samples are determined. The presence of ACI is detected based on the correlations of the filtered I and Q samples and the power of the input I and Q samples. If ACI is present, then whether the ACI is from a higher frequency channel or a lower frequency channel is determined based on one or more of the correlations. The input I and Q samples are filtered with a second filter response that is adjusted based on the detection of ACI. | 09-18-2008 |
| 20090003427 | BURSTY INTERFERENCE SUPPRESSION FOR COMMUNICATIONS RECEIVERS - Techniques are provided for suppressing interference by taking into account the possible bursty nature of co-channel interference in a communication system. In an aspect, interference levels are separately computed for first and second data portions of a desired signal. The computed interference levels may be used to scale the corresponding data portions for subsequent processing. | 01-01-2009 |
| 20090245192 | Reconfigurable Wireless Modem Sub-Circuits To Implement Multiple Air Interface Standards - A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard. | 10-01-2009 |
| 20090245423 | De-Interlever That Simultaneously Generates Multiple Reorder Indices - A de-interleaver involves logic that receives a seed and that simultaneously generates from the seed a plurality of reorder indices. The plurality of reorder indices is usable for de-interleaving an incoming stream of interleaved code bits. Each plurality of simultaneously generated reorder indices generated corresponds to a set of simultaneously received code bits in the incoming stream. The reorder indices are converted into physical addresses in parallel and these physical addresses are used to store the set of code bits into a memory. Code bits for multiple sub-packets of different sub-packet sizes are typically present in memory at the same time. The code bits are then read out of memory to form an outgoing stream of de-interleaved code bits. The de-interleaver has a pipelined architecture such that sets of code bits are written into the memory at the same rate that sets of code bits are received onto the de-interleaver. | 10-01-2009 |
| 20090245430 | EFFICIENT PARALLEL SUB-PACKET DECODING USING MULTIPLE DECODERS - A configurable decoder within a receiver (for example, within a wireless communication device) includes numerous decoders. In one mode, the multiple decoders are used to decode different sub-packets of a packet. When one decoder completes decoding the last sub-packet assigned to it of the packet, then that decoder generates a packet done indication. A control circuit receives the packet done indications, and when all the decoders have generated packet done indications then the control circuit initiates an action. In one example, the action is the interrupting of a processor. The processor responds by reading status information from the control circuit, thereby resetting the interrupt. End-of-packet markers are usable to generate packet done indications and to generate EOP interrupts. Similarly, end-of-group markers are usable to generate group done indications and to generate EOG interrupts. The decoder block is configurable to process sub-packets of a packet using either one or multiple decoders. | 10-01-2009 |
| 20110105070 | Direct conversion receiver architecture - A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus. | 05-05-2011 |
