| Patent application number | Description | Published |
|---|
| 20090195280 | INTEGRATED CIRCUIT HAVING A MEMORY WITH A PLURALITY OF STORAGE CELLS OF SYNCHRONOUS DESIGN AND CONNECTED TO CLOCK GATING UNITS - In a memory area having portions of predictable access frequency, such as in a memory area of a real time clock unit, a synchronous design may be implemented by associating storage cells of identical access frequency with a clock gating mechanism, thereby reducing power consumption. Hence, the synchronous design of the real time clock unit may provide reduced implementation effort and enhanced verification capability. | 08-06-2009 |
| 20090197377 | ESD POWER CLAMP WITH STABLE POWER START UP FUNCTION - A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps. | 08-06-2009 |
| 20090243663 | ANALOG COMPARATOR COMPRISING A DIGITAL OFFSET COMPENSATION - A digital compensation of an input stage of a comparator may be achieved by providing switched load elements, which may be appropriately connected to the differential input pair of the comparator in order to match transistor characteristics of the input pair and also match the load value of the input stage. Thus, enhanced offset behavior may be accomplished without providing an external signal and/or without requiring complex reference voltages/currents. | 10-01-2009 |
| 20090273053 | SEMICONDUCTOR DEVICE INCLUDING ANALOG CIRCUITRY HAVING A PLURALITY OF DEVICES OF REDUCED MISMATCH - In an analog circuit portion, a systematic mismatch between a plurality of circuit elements may be reduced in view of a technology gradient by appropriately positioning the unit devices of the circuit elements so as to obtain a similar response of the circuit elements with respect to the gradient. For example, the spatial relationship of adjacent unit devices belonging to the same circuit element along an arbitrary lateral direction may be the same as the spatial relationship of adjacent unit devices of another circuit element. | 11-05-2009 |
