Chaiyasit

Chaiyasit Kumtornkittikul, Kanagawa-Ken JP

Patent application number	Description	Published
20090085056	OPTICAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - According to an aspect of the present invention, there is provided an optical semiconductor device, comprising, a first AlN clad-layer, a first nitride semiconductor guide-layer formed on the first AlN clad-layer, refractive index of the first nitride semiconductor guide-layer being larger than refractive index of the first AlN clad-layer, a nitride semiconductor core-layer formed on the first nitride semiconductor guide-layer, refractive index of the nitride semiconductor core-layer being larger than refractive index of the first AlN clad-layer and smaller than refractive index of the first nitride semiconductor guide-layer, a second nitride semiconductor guide-layer formed on the nitride semiconductor core-layer, refractive index of the second nitride semiconductor guide-layer being larger than refractive index of the nitride semiconductor core-layer, a second AlN clad-layer formed on the second nitride semiconductor guide-layer.	04-02-2009

Patent application number	Description	Published
20100122038	METHODS AND APPARATUSES FOR IMPROVING SPECULATION SUCCESS IN PROCESSORS - Methods and apparatuses are disclosed that allow for improved speculation success in execute ahead microprocessors. In some embodiments, the method may include speculatively executing a first thread of a program code while a second thread of the program code is executing, determining if a load request is serviceable from a cache line within a cache, and in the event that the load request is serviceable from the cache line, associating a first indicator bit with the cache line. The method also may include determining whether the cache line associated with the first indicator bit has been evicted, and in the event that the cache line is evicted, allowing speculative execution of the first thread to continue.	05-13-2010

Patent application number	Description	Published
20080288834	VERIFICATION OF MEMORY CONSISTENCY AND TRANSACTIONAL MEMORY - A system for efficiently verifying compliance with a memory consistency model includes a test module and an analysis module. The test module may coordinate an execution of a multithreaded test program on a test platform. If the test platform provides an indication of the order in which writes from multiple processing elements are performed at shared memory locations, the analysis module may use a first set of rules to verify that the results of the execution correspond to a valid ordering of events according to a memory consistency model. If the test platform does not provide an indication of write ordering, the analysis module may use a second set of rules to verify compliance with the memory consistency model. Further, a backtracking search may be performed to find a valid ordering if such ordering exists or show that none exists and, hence, confirm whether or not the results comply with the given memory consistency model.	11-20-2008