Patent application number | Description | Published |
20090283898 | DISABLING ELECTRICAL CONNECTIONS USING PASS-THROUGH 3D INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect. | 11-19-2009 |
20100172059 | OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS FOR INTEGRATED CIRCUITS - Integrated circuits, memories, protection circuits and methods for protecting against an over-limit electrical condition at a node of an integrated circuit. One such protection circuit includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit electrically coupled to a reference voltage and further electrically coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition for the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit. | 07-08-2010 |
20120309128 | DISABLING ELECTRICAL CONNECTIONS USING PASS-THROUGH 3D INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect. | 12-06-2012 |
20130050886 | OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS AND METHODS - Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected. | 02-28-2013 |
20130214421 | DISABLING ELECTRICAL CONNECTIONS USING PASS-THROUGH 3D INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect. | 08-22-2013 |
20140218830 | OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS FOR INTEGRATED CIRCUITS - Protection circuits and methods for protecting an integrated circuit against an over-limit electrical condition are provided. One example includes a snapback circuit having at least a portion formed in an isolated doped well region and configured to switch to a low impedance state in response to an input exceeding a trigger condition and further having a control circuit coupled to a reference voltage and further coupled to the isolated doped well region and the portion of the snapback circuit formed in the doped well region. The control circuit includes an impedance adjustable in response to a control signal and configured to adjust an isolated doped well impedance in which at least a portion of the snapback circuit is formed relative to the reference voltage. A modulated trigger and hold condition tot the snapback circuit can be set according to a control signal adjusting an electrical impedance of the control circuit. | 08-07-2014 |
20140240883 | OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS AND METHODS - Apparatuses and methods for protecting a circuit from an over-limit electrical condition are disclosed. One example apparatus includes a protection circuit coupled to a circuit to be protected. The circuit to be protected is coupled to a pad node. The protection circuit is configured to conduct current from the pad node to a reference voltage node to protect the circuit from an over-limit electrical condition. The protection circuit has a trigger circuit coupled to the pad node and configured to trigger a shunt circuit to conduct current from the pad node to the reference voltage node responsive to a voltage provided to the pad node having a voltage exceeding a trigger voltage. In some embodiments, the trigger circuit is matched to the circuit being protected. | 08-28-2014 |
20140268438 | APPARATUSES AND METHOD FOR OVER-VOLTAGE EVENT PROTECTION - Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage. | 09-18-2014 |
20140319697 | DISABLING ELECTRICAL CONNECTIONS USING PASS-THROUGH 3D INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Pass-through | 10-30-2014 |
Patent application number | Description | Published |
20130050887 | COMBINATION ESD PROTECTION CIRCUITS AND METHODS - Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. In an example method, a thyristor is triggered to conduct current from a signal node to a reference voltage node using leakage currents provided by a transistor formed in a semiconductor doped well shared with the base of the thyristor. The leakage currents are responsive to a noise event (e.g., electrostatic discharge (ESD) event) at the signal node, and increase the voltage of the semiconductor doped well to forward bias the base and the collector of the thyristor. The triggered thyristor conducts the current resulting from the ESD event to the reference voltage node. | 02-28-2013 |
20130128399 | APPARATUSES, CIRCUITS, AND METHODS FOR PROTECTION CIRCUITS FOR DUAL-DIRECTION NODES - Apparatuses, circuits, and methods are disclosed for biased protection circuits for dual-direction nodes. In one such example apparatus, a protection circuit is coupled to a dual-direction node, and includes a positive protection component and a negative protection component. The protection circuit is configured to protect the dual-direction node during an over-limit electrical condition. The protection circuit is configured to control a turn-on condition of the protection circuit. | 05-23-2013 |
20140104733 | COMBINATION ESD PROTECTION CIRCUITS AND METHODS - Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. In an example method, a thyristor is triggered to conduct current from a signal node to a reference voltage node using leakage currents provided by a transistor formed in a semiconductor doped well shared with the base of the thyristor. The leakage currents are responsive to a noise event (e.g., electrostatic discharge (ESD) event) at the signal node, and increase the voltage of the semiconductor doped well to forward bias the base and the collector of the thyristor. The triggered thyristor conducts the current resulting from the ESD event to the reference voltage node. | 04-17-2014 |
Patent application number | Description | Published |
20100282524 | TOUCH CONTROL SYSTEM AND METHOD FOR LOCALISING AN EXCITATION - A touch control system and method having an interaction means between a user and a system, at least two transforming means for transforming an excitation of the interaction means into respective signals and a signal processing means configured to determine the position on the interaction means where the excitation occurred. To simplify such a system, the invention uses a signal processing means, which is configured such that signatures are determined based on a comparison of at least one parameter of the respective signals. Also, a touch control system, wherein the transformation means are positioned within a housing with limber sidewalls. | 11-11-2010 |
20110047494 | Touch-Sensitive Panel - The invention relates to a touch sensitive panel comprising a single interaction means with at least a first and a second interaction area, wherein the interaction means is transparent in the first interaction area, at least one transforming means for transforming a mechanical, in particular pressure, excitation of the at least first and/or second interaction area of the interaction means into respective signals, and a processing means configured to identify the position of the excitation based on the signals. It furthermore relates to a device comprising such touch sensitive panel. It furthermore relates to an improved drag and drop method. | 02-24-2011 |
20130257821 | METHOD FOR DETERMINING A TOUCH EVENT AND TOUCH SENSITIVE DEVICE - The invention relates to a method for determining a touch event provided by a user on an interaction surface of a touch sensitive device comprising the steps of: sensing a raw signal by a transducer, in particular by a piezo-electric transducer and low-pass filtering the sensed signal, segmenting the filtered raw signal into a baseline signal and at least one useful signal, and analyzing the at least one useful signal to determine properties of the touch event. | 10-03-2013 |