| Patent application number | Description | Published |
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| 20090027957 | VOLTAGE SUPPLY CIRCUIT AND FLASH MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF SUPPLYING OPERATING VOLTAGE - A voltage supply circuit includes a voltage generator and a controller. The voltage generator is configured to pump an externally input voltage and store the pumped external voltage as a first voltage having a set voltage level, before power-up begins, or pump the external voltage, add the pumped voltage to the stored voltage, and output the added voltage as an operating voltage. The controller is configured to output a first control signal to drive the voltage generator or stop operation of the voltage generator, according to an operating state. | 01-29-2009 |
| 20090052247 | FUSE CIRCUIT AND FLASH MEMORY DEVICE HAVING THE SAME - A fuse circuit in a flash memory device is disclosed. The fuse circuit includes a plurality of memory cells turned on/off by a first voltage in accordance with program state, a switching circuit configured to switch in response to a control signal, thereby transmitting a verifying signal for verifying program of the memory cell to the memory cell, and a cell controller configured to output the verifying signal for controlling program, verification and erase of the memory cells and the control signal. | 02-26-2009 |
| 20090122615 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - Program voltages of a non-volatile memory device are controlled variably according to a program/erase operation count. The non-volatile memory device includes a program voltage supply unit for applying a program voltage to a memory cell, a program/erase count storage unit for storing a total program/erase operation count of the non-volatile memory device, a program start voltage storage unit for storing levels of program start voltages to be differently supplied according to the program/erase operation count, and a program voltage controller for controlling the program start voltage according to the program/erase operation count. | 05-14-2009 |
| 20090122616 | NON-VOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING A BULK VOLTAGE THEREOF - A threshold voltage of a non-volatile memory device is compensated by a voltage supplier and a controller. The voltage supplier supplies a set voltage to a bulk of a memory cell array, including memory cells, at the time of a read operation of the memory cells. The controller controls the voltage supplier to set and supply a bulk voltage depending on a threshold voltage change of the memory cells. | 05-14-2009 |
| 20090172482 | METHODS FOR PERFORMING FAIL TEST, BLOCK MANAGEMENT, ERASING AND PROGRAMMING IN A NONVOLATILE MEMORY DEVICE - Methods for performing a fail test, block management, erase operations and program operations are used in a nonvolatile memory device having a block switch devoid of a fuse and a PMOS transistor. A method for performing a fail test in a nonvolatile memory device includes performing a fail test for a memory cell block; storing good block information in a block information store associated with the corresponding block when the memory cell block is a good block; and repeating the performing and storing steps for all memory cell blocks. | 07-02-2009 |
| 20090238007 | METHOD OF SUPPLYING AN OPERATING VOLTAGE OF A FLASH MEMORY DEVICE - A method of supplying an operating voltage of a flash memory device includes supplying an operating voltage to a word line selected according to an input address, and changing a pass voltage according to a change of the operating voltage level. The pass voltage is supplied to unselected word lines other than the selected word line. | 09-24-2009 |
| 20100284222 | FUSE CIRCUIT AND FLASH MEMORY DEVICE HAVING THE SAME - A flash memory device includes a main cell array configured to have main memory cells for storing data and a redundancy cell array configured to have redundancy memory cells for repairing a failed memory cell of the main cell array. A page buffer circuit is configured to perform a program operation, a verifying operation and a read operation on the main cell array and the redundancy cell array. A repair circuit includes fuse circuits having fuse memory cells each of which is programmed in response to address information. The repair circuit is operated in response to a program state of the fuse memory cells and output a repair signal. A data input/output controller is configured to control input/output of data to/from the main memory cell or the redundancy memory cell in accordance with the repair signal outputted by the repair circuit. | 11-11-2010 |
| Patent application number | Description | Published |
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| 20090251983 | SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF REDUCING GROUND NOISE - An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each of the first driving signal driving units such that a predetermined time difference is generated between an enable timing of the first driving signal and an enable timing of the second driving signal, a plurality of sense amplifier driving units, each of which generates a first driving level and a second driving level according to the first driving signal and the second driving signal, and a plurality of sense amplifiers that are provided for respective bit line pairs, and each include first type switching elements operating according to the first driving level and second type switching elements operating according to the second driving level. | 10-08-2009 |
| 20090257302 | Semiconductor memory apparatus capable of reducing ground noise - An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each of the first driving signal driving units such that a predetermined time difference is generated between an enable timing of the first driving signal and an enable timing of the second driving signal, a plurality of sense amplifier driving units, each of which generates a first driving level and a second driving level according to the first driving signal and the second driving signal, and a plurality of sense amplifiers that are provided for respective bit line pairs, and each include first type switching elements operating according to the first driving level and second type switching elements operating according to the second driving level. | 10-15-2009 |
| 20100008137 | NONVOLATILE MEMORY DEVICE AND PROGRAM OR ERASE METHOD USING THE SAME - A nonvolatile memory device includes a comparison unit configured to compare a reference voltage and a voltage of each of a plurality of nodes of a sample memory cell string, a state storage unit configured to store state information of each of memory cells depending on the corresponding comparison result of the comparison unit, and a high voltage generation unit configured to change a program start voltage depending on data stored in the state storage unit. | 01-14-2010 |
