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Cha, Gyeonggi-Do
An-Ki Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090317215 | VACUUM CHAMBER FOR PROCESSING SUBSTRATE AND APPARATUS INCLUDING THE SAME - A vacuum chamber for processing a substrate includes: a chamber body; and a chamber lid combined with the chamber body, wherein the chamber lid comprises: a frame having a plurality of openings; and a plurality of plates combined with the plurality of openings. | 12-24-2009 |
Byung-Cheol Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090101811 | METHOD OF AND APPARATUS FOR ANALYZING IONS ADSORBED ON SURFACE OF MASK - A method of analyzing ions adsorbed on a surface of a mask for pattern formation of a semiconductor device, and an apparatus using the same are disclosed. The ion analyzing method includes: filling a heating container within a main chamber with a predetermined amount of a solvent; immersing a mask in the solvent-filled heating container; raising an internal pressure of the chamber to a predetermined level by supplying gas into the chamber; separating ions from a surface of the mask by heating the solvent within the heating container at a predetermined temperature for a predetermined period; and analyzing the ions by collecting the solvent. | 04-23-2009 |
Cheol Yong Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100324175 | Polymer for Ultra-High Strength Concrete Admixture and Method for Preparing the Same - Disclosed are a polymer for ultra-high strength concrete admixture and a method for preparing the same, more specifically, a polymer for ultra-high strength concrete admixture prepared by polymerizing two or more copolymers based on unsaturated organic monomers having urethane derivatives, and and a method for preparing the same. Also, the concrete admixture comprising the polymer exhibits high water-reducing ability, thus improving workability and strength of the concrete composition. In addition, the concrete admixture exhibits defoaming capability, thus enabling easy control of air amount of the concrete composition without using any defoaming agent. | 12-23-2010 |
| 20120046393 | Nano-hybrid Concrete Chemical Admixture for Chloride Invasion Resistance Consisting of Layered Double Hydroxide/Polyurethane Copolymer - The present invention relates to a chloride penetration resistant nano-hybrid concrete chemical admixture comprising layered double hydroxide and polyurethane copolymer. More specifically, nano-hybrid concrete chemical admixture obtained by combining the two compounds at a nano-scale, the layered double hydroxide which exhibits resistance to chloride penetration, and polyurethane copolymer which entails an excellent water reducing ability, durability and workability. In addition, the inorganic/organic hybrid material described herein exhibits high water reducing ability, improved resistance to chloride penetration, and thus can be used as chloride penetration resistant concrete chemical admixture for marine concretes. | 02-23-2012 |
Choong-Yul Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090153259 | DIGITALLY CONTROLLED OSCILLATOR (DCO) - A digitally controlled oscillator (DCO) includes a current generator which generates an electric current having a magnitude corresponding to an input signal, and a digitally controlled oscillating unit which generates an oscillating frequency based on an inductance which varies according to the magnitude of the electric current generated by the current generator. | 06-18-2009 |
| 20090174493 | ADJUSTABLE INDUCTOR AND WIDEBAND VOLTAGE CONTROLLED OSCILLATOR - An adjustable inductor includes a first conductor line to receive an alternating current (AC) signal, a second conductor line configured in a loop arrangement, to generate an inducting current upon receiving the AC signal at the first conductor line, and a switch to adjust an inductance of the first conductor line by switching a loop connection of the second conductor line according to an external control signal. | 07-09-2009 |
Dae Won Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090281301 | Manufacturing Process of 2' ,2' - Difluoronucleoside and Intermediate - The present invention relates to more improved process for preparing 2′-deoxy-2′,2′-difluoronucleoside and its intermediate. The present invention provide a process for preparing an erythro enantiomer in greater than 98% purity, comprising forming a lactone ring by hydrolyzing ethyl (3RS)-2,2-difluoro-3-hydroxy-3-(2,2-dimethyloxolan-4-yl)propionate is hydrolyzed in the presence of hydrolysis reagents selected from acetic acid or chloroacetic acid, water and a mixture of organic solvents selected from the group comprising acetonilrile, dioxane, tetrahydrofuran or toluene, introducing a substituted benzoyl protecting group at the 3-position and 5-position, and recrys- tallizing said erythro enantiomer. Further, the present invention provides a process for selectively preparing, in greater than 99% purity, a beta-anomer 2′-deoxy-2′,2′-difluoronucleoside at the 3′-position and 5′-position that are protected by a substituted benzoyl in a 2:3 alpha/beta anomeric ratio. | 11-12-2009 |
| 20100113556 | NOVEL CRYSTAL FORMS OF PYRROLYLHEPTANOIC ACID DERIVATIVES - The present invention provides novel crystalline forms D1 and D2 of [R—(R*,R*)]-2-(4-fluorophenyl)-β,δ-dihydroxy-5-(1-methylethyl)-3-phenyl-4-[(phenylamino)carbonyl]-1H-pyrrole-1-heptanoic acid hemicalcium salt, and hydrates thereof. The crystalline forms D | 05-06-2010 |
Du-Jin Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100290357 | APPARATUS AND METHOD OF DETERMINING MAXIMUM SEGMENT SIZE OF DATA CALL IN MOBILE COMMUNICATION SYSTEM - An apparatus and method for determining a maximum segment size (MSS) in a mobile communication system. When the portable terminal accesses a multimedia service server through a data call, the method includes confirming whether or not a maximum segment size (MSS) of the server is stored; if the MSS is stored, the server is accessed using the MSS; and if the MSS is not stored, determining the MSS of the server through a ping procedure. | 11-18-2010 |
Guy-Ho Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080239757 | LIQUD CRYSTAL DSIPLAY DEVICE HAVING A CONTAINER MODULE WITH A NOVEL STRUCTURE - A liquid crystal display has a mold frame divided into several parts. The liquid crystal display device includes a display unit for displaying an image, a back light assembly having a light source for generating a light, a light guiding plate for guiding the light, and a light focusing portion for focusing the light, and a mold frame divided into a first frame and a second frame. The mold frame receives the display unit and the back light assembly. The first frame receives the light guiding plate and the light focusing portion and the second frame receives the light source. A reflection sheet is integrally formed at an inner surface of the second frame so as to perform the function of a lamp reflector. Accordingly, a lamp cover is not required so that the number of parts and the manufacturing cost are reduced. A lamp can be exchanged by simply separating the second frame from the mold frame, so the fault of the light source caused by the friction with other elements is reduced when exchanging the lamp. | 10-02-2008 |
Hwa Jin Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20120026918 | METHOD AND SYSTEM OF MANAGING NEIGHBOR RELATION TABLE IN WIRELESS COMMUNICATION SYSTEM HAVING SELF-ORGANIZING NETWORK FUNCTION - Provided is a method of managing a neighbor relation table by a base station in a wireless communication system having a self-organizing network function, which includes receiving a neighbor base station report from a terminal; comparing the neighbor base station report with a stored neighbor relation table; calculating a statistic value of a new base station when the new base station is present in the comparison step; and adding the new base station to the stored neighbor relation table when the statistic value is equal to or greater than a first reference value. | 02-02-2012 |
Hye Yeon Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20120087001 | ELECTRONIC PAPER DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides an electronic paper display device including: a base substrate; rotating balls positioned on the base substrate and consisting of hemispheres of different colors; and a barrier structure for separating the rotating balls on the base substrate and having cavities in which the rotating balls are positioned and an oil supply passage connected to the cavities to supply oil to the cavities. | 04-12-2012 |
Hyun-Sik Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100157856 | METHOD AND APPARATUS FOR REDUCING A CHANNEL DEVIATION IN A MOBILE COMMUNICATION TERMINAL - A transmitting apparatus and a transmitting method for improving a channel deviation in a mobile communication terminal are provided. The transmitting apparatus includes a power amplifier for amplifying a transmitting signal by a predetermined level and outputting an amplified transmitting signal, a controller for outputting a signal to control a variable capacitor according to a channel of the transmitting signal and a phase transition unit for varying each capacitance value according to a control of the controller and transiting a phase of a signal outputted from the power amplifier. | 06-24-2010 |
Ii-Hoon Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110269935 | METHOD FOR PREPARING POLYARYLENE SULFIDE WITH REDUCED FREE IODINE CONTENT - The present invention relates to a method for preparing polyarylene sulfide with a reduced free iodine content. More specifically, the method for preparing polyarylene sulfide includes: (a) polymerizing reactants including a diiodo aromatic compound and a sulfur compound to form a polyarylene sulfide; and (b) maintaining the polyarylene sulfide product at 100 to 260° C. for heat-setting. The preparation method of the present invention effectively reduces the free iodine content of the polyarylene sulfide to prevent potential corrosion of facilities for the subsequent process and improves the properties of the polyarylene sulfide product such as thermal stability, so the method can be usefully applied to industrial fields in regard to the preparation of polyarylene sulfide. | 11-03-2011 |
Il-Hoon Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090203872 | MANUFACTURING PROCESS FOR POLY (ARYLENE SULPHIDE) - This invention relates to a method of preparing poly(arylene sulfide) (PAS) from an iodo compound and a sulfur compound, and more particularly, to a method of preparing PAS, including adding a sulfur-containing polymerization terminator when PAS is produced using an iodo compound as an intermediate. Thereby, in final PAS, the residual iodine content may be maintained at the same level or decreased and other properties may be maintained at equal or superior levels, thanks to the use of the sulfur-containing polymerization terminator, which is much lower in price than conventional polymerization terminators. | 08-13-2009 |
| 20100185031 | MANUFACTURING PROCESS FOR IODINATED AROMATIC COMPOUNDS - Disclosed is a method for preparing an iodinated aromatic compound. More specifically, disclosed is a method of preparing an iodinated aromatic compound by iodinating an aromatic compound in the presence of oxygen over a zeolite catalyst, in which the aromatic compound and its monoiodo compound, as raw materials, are allowed to react with iodine. In comparison with a method in which only the aromatic compound is used as a raw material without adding the monoiodo compound, the disclosed method can increase the productivity of diiodo compounds and the selectivity to a p-diiodo compound and, at the same time, suppress side reactions, thus lengthening the life span of the catalyst. | 07-22-2010 |
| 20100222617 | METHOD OF PREPARING IODINATED AROMATIC COMPOUNDS - The present invention relates to a method of preparing iodinated aromatic compounds, and more preferably a method of preparing iodinated aromatic compounds comprising a step of iodinating a reactant including an aromatic compound, a di-iodo aromatic compound or water, and iodine (I2) in the presence of a zeolite catalyst and oxygen. The method of the present invention has an advantage that by iodination of a reactant including the aromatic compound, and the di-iodo aromatic compound or water in the presence of the zeolite catalyst and oxygen, the temperature of the iodinating reactor can be controlled reliably and constantly, thereby resulting in improved productivity per unit weight of catalyst and inhibition of a side reaction in accordance with suppression of producing impurities. In addition, the productivity of the iodinated aromatic compound, preferably the di-iodo aromatic compound, more preferably a p-di-iodo aromatic compound can be improved, and thus can be widely used in the preparation of a di-iodo aromatic compound such as a p-di-iodo aromatic compound. | 09-02-2010 |
| 20110245550 | PROCESS FOR PREPARING IODINATED AROMATIC COMPOUNDS - The present invention relates to a process for preparing iodinated aromatic compounds. Particularly, the present invention comprises the step of performing the iodination of a non-halogenated aromatic compound, a monoiodo aromatic compound, a diiodo aromatic compound, and iodine in the presence of a zeolite catalyst under oxygen atmosphere. | 10-06-2011 |
| 20110257363 | METHOD FOR PREPARING POLYARYLENE SULFIDE - The present invention relates to a method for preparing polyarylene sulfide, in which the polyarylene sulfide is prepared by a polymerization reaction of reactants including a diiodo aromatic compound and a sulfur compound, the method including: further adding 0.01 to 10.0 wt. % of diphenyl disulfide with respect to the weight of the polyarylene sulfide to the reactants to form the polyarylene sulfide having a melting point of 265 to 320° C. | 10-20-2011 |
Jae Hoon Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090070061 | SEMICONDUCTOR MEMORY DEVICE INCLUDING TEST MODE CIRCUIT - A semiconductor memory device having a test mode circuit is presented which includes: a mode setting unit, in response to an external command and a first address signal for a mode set, providing a mode register set signal corresponding to predetermined mode setting; and a test mode circuit, in response to the mode register set signal and a second address signal for test enable control in an initial operation, performing test mode enable; the test mode circuit, in response to the mode register set signal and a third address signal for test item selection in the test mode enable state, outputting a test mode item signal; and the test mode circuit, in a subsequent operation, receiving the fed-back test mode item signal to maintain the test mode enable state. | 03-12-2009 |
| 20120008451 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first group configured to include a first bank and a second bank; a second group configured to include a third bank and a fourth bank; an address strobe pulse generating unit configured to generate an address strobe pulse signal for activating the first group and the second group in response to a first bank address and a command signal; and a strobe signal generating unit configured to generate a strobe signal that selects a bank from the first group and the second group in response to the address strobe pulse signal and a second bank address. | 01-12-2012 |
Jae Won Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100302866 | METHOD OF TESTING FOR A LEAKAGE CURRENT BETWEEN BIT LINES OF NONVOLATILE MEMORY DEVICE - A method of testing for a leakage current between bit lines of a nonvolatile memory device includes providing the nonvolatile memory device with a page buffer having first and second bit lines coupled thereto, precharging the first bit line to a first voltage, supplying a second voltage to the second bit line, floating the second bit line and evaluating the second bit line for a set time period, and detecting a voltage level of the second bit line and outputting a test result of testing for the leakage current between the first and second bit lines by the page buffer. | 12-02-2010 |
Jae Wook Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080267937 | Compositions for Preventing Plant Disease Comprising Bacillus Subtilis Kccm 10639 or Kccm 10640 and Methods of Preventing Plant Disease by Using Them - The present invention relates to a composition for controlling plant diseases, which comprises novel bacterial strain | 10-30-2008 |
Jin-Youp Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110001526 | DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a phase comparison unit configured to compare a reference clock with a feedback clock and to output a phase comparison signal, a clock delay unit configured to delay a first reference clock in response to the phase comparison signal, to output a first delay locked clock, to delay one of the first delay locked clock and a second reference clock according to a frequency information signal, and to output a second delay locked clock, a delay locked clock generating unit configured to output a delay locked clock as a phase-mixed clock of the first delay locked clock and the second delay locked clock, the first delay locked clock, or the second delay locked clock in response to the frequency information signal and a delay transfer signal, and a delay replica model unit configured to reflect a delay condition of the reference clock. | 01-06-2011 |
| 20110158025 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a sensing unit configured to sense whether a value of a programming sensing node is within a predefined range, a fuse connected to the programming sensing node, a programming voltage supplying unit configured to supply a programming voltage to the programming sensing node, and a transferring unit configured to transfer the value of the programming sensing node in response to the sensing result of the sensing unit. | 06-30-2011 |
Junghak Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090208983 | Diagnose device for measuring the ratio of proteins with similar structure - The present invention relates to a diagnostic device for measuring the ratio of similar structural proteins among the proteins secreted in a liquid test sample taken from diagnosis subject. In further detail, the test device according to the present invention comprises detection marker-antibody conjugate recognizing the same site on two or more similar structural proteins and a detection zone in which antibody specifically recognizes each of said proteins via formation of sandwich type complex, wherein said antibodies form a set, and the present Invention relates to a diagnostic device for early diagnosis of polycystic ovary syndrome, abnormal pregnancy, prostatic carcinoma etc. based on determination of the ratio of follicle stimulating hormone and luteinizing hormone in case of polycystic ovary syndrome, the ratio between hCG isomers in case of abnormal pregnancy, and the ratio of prostate-specific antigens (PSA) in case of prostatic carcinoma. | 08-20-2009 |
Ki Bon Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100072598 | SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip. | 03-25-2010 |
Kwang-Sik Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100149745 | INSTALLING STRUCTURE OF MEMORY FOR PORTABLE TERMINAL - An installing structure of a memory for a portable terminal provides easy install and removal. The structure includes a main board and a sub-board coupled to the main board. A chip-type memory is coupled to the sub-board, and an electrical coupling unit transfers electrical signals between the main board and the sub-board. The memory installing structure of the portable terminal provides convenience by facilitating the replacement of the memory for repair or as an upgrade of capacity. | 06-17-2010 |
Kyeong-Hoe Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110112309 | PREPARATION PROCESS USEFUL IN SYNTHESIS OF ATORVASTATIN - The present invention relates to a preparation process useful in synthesis of atorvastatin, more particularly a process for preparing atorvastatin is effective in treating hyperlipemia, comprising protecting the dihydroxy group at C3 and C5 positions of the starting material cis-t-butyl-6-substituted-3,5-dihydroxy-hexanoate with trialkyl orthoformate, reducing the terminal nitro or cyano group to amine group, performing JV-alkylation by sequentially reacting with ethyl 4-fluorobenzene-2-haloacetate and isobutyryl chloride, cyclizing with JV,3-diphenylpropynamide, and performing deprotection and hydrolysis. | 05-12-2011 |
Kyung-Hoi Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100272820 | Preparation Method of Sustained-Release Microcapsules Having Good Initial Burst Inhibiting Property and the Microcapsules Thereby - Disclosed is a method for preparing a longer sustained-release formulation containing bioactive substances. More particularly, the present invention provides a method for preparing longer sustained-release microcapsules comprising: adding an emulsion including bioactive substances, biocompatible polymer and polyvinylpyrrolidone to an aqueous solution. | 10-28-2010 |
| 20110200679 | METHOD FOR MANUFACTURING SUSTAINED RELEASE MICROSPHERE BY SOLVENT FLOW EVAPORATION METHOD - The present invention relates to a method for preparing a sustained-release microsphere which can control the long-term release of a drug. More particularly, as the preparation of a microsphere in which a drug is loaded in a carrier comprising a biodegradable polymer, the present invention relates to a method for preparing a sustained-release microsphere wherein a solvent intra-exchange evaporation method by means of co-solvent is used for suppressing the initial burst release of physiologically active substance, to release the physiologically active substance in the body continuously and uniformly. | 08-18-2011 |
Sang Hyun Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20110316825 | ORGANIC ELECTROLUMINESCENCE DISPLAY - Disclosed herein is an organic electroluminescence display. The organic electroluminescence display includes: a plurality of pixels arranged in a matrix format on a display panel and configured of first to N+K-th rows; a plurality of first data lines connected to pixels each in the same column of pixels in the first to N-th rows; a plurality of second data lines connected to pixels each in the same column of pixels in the k+1-th to N+K-th rows; and a plurality of pixel driving buffers sensing time constants of the second data lines and compensating for data currents according to the number of sensed time constants to drive the respective corresponding first data lines with the compensated data currents. The organic electroluminescence display can reduce operation deviation between the pixels according to parasitic components of the data lines. | 12-29-2011 |
Sang Yeob Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090305922 | LUBRICATING OIL COMPOSITION FOR AUTOMOBILE TRANSMISSION AND LUBRICATING METHOD USING SAME - The present invention relates to an automatic transmission lubricating oil composition, and particularly to an automatic transmission lubricating oil composition comprising an oil of lubricating viscosity, an ashless dispersant, an anti-oxidant, a phosphorus-based anti-wear agent and a friction-modifier, wherein more than 310 ppm of phosphorus is contained, thereby being useful for lubricating or operating an automatic transmission comprising a transmission clutch using a slip lock-up torque converter and a paper based clutch material and a planetary gear system, especially six-speed automatic transmission. | 12-10-2009 |
Seon Yong Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090114978 | VERTICAL TRANSISTOR AND METHOD FOR FORMING THE SAME - A vertical transistor and a method for forming the same. The vertical transistor includes a semiconductor substrate having pillar type active patterns formed on a surface thereof; first junction regions formed in the surface of the semiconductor substrate on both sides of the active patterns; screening layers formed on sidewalls of the first junction regions; second junction regions formed on upper surfaces of the active patterns; and gates formed on sidewalls of the active patterns including the second junction regions to overlap with at least portions of the first junction regions. | 05-07-2009 |
| 20120021576 | VERTICAL TRANSISTOR AND METHOD FOR FORMING THE SAME - A vertical transistor and a method for forming the same. The vertical transistor includes a semiconductor substrate having pillar type active patterns formed on a surface thereof; first junction regions formed in the surface of the semiconductor substrate on both sides of the active patterns; screening layers formed on sidewalls of the first junction regions; second junction regions formed on upper surfaces of the active patterns; and gates formed on sidewalls of the active patterns including the second junction regions to overlap with at least portions of the first junction regions. | 01-26-2012 |
Sun Shin Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100311142 | Novel Hydrogenases Isolated from Thermococcus SPP., Genes Encoding the Same, and Methods for Producing Hydrogen Using Microorganisms Having the Genes - The present invention relates to novel hydrogenases isolated from novel hyperthermophilic strains belonging to | 12-09-2010 |
Taeho Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100055891 | DUAL GATE STRUCTURE, FABRICATION METHOD FOR THE SAME, SEMICONDUCTOR DEVICE HAVING THE SAME, AND SEMICONDUCTOR DEVICE FABRICATION METHOD - In one embodiment, a semiconductor device includes at least two stacked gate structures formed on a substrate. The two stacked gate structures each include a semiconductor layer and a metal layer over the semiconductor layer. The two stacked gate structures on the substrate are characterized by differential intermediate layers, one of the two structures including an ohmic layer and the other of the two structures not including an ohmic layer. | 03-04-2010 |
Tae-Ho Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090267132 | GATE STRUCTURES IN SEMICONDUCTOR DEVICES - A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion preventing layer pattern on the metal ohmic layer pattern, an amorphous layer pattern on the diffusion preventing layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability. | 10-29-2009 |
| 20090315091 | GATE STRUCTURE, AND SEMICONDUCTOR DEVICE HAVING A GATE STRUCTURE - A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer | 12-24-2009 |
| 20110171818 | METHODS OF FORMING A GATE STRUCTURE - A method of forming a gate structure can be provided by forming a tunnel insulation layer on a substrate and forming a floating gate on the tunnel insulation layer. A dielectric layer pattern can be on the floating gate and a control gate can be formed on the dielectric layer pattern, which can be provided by forming a first conductive layer pattern on the dielectric layer pattern. A metal ohmic layer pattern can be formed on the first conductive layer pattern. A diffusion preventing layer pattern can be formed on the metal ohmic layer pattern. An amorphous layer pattern can be formed on the diffusion preventing layer pattern forming a second conductive layer pattern on the amorphous layer pattern. The floating gate can be further formed by forming an additional first conductive layer pattern on the tunnel insulation layer. An additional metal ohmic layer pattern can be formed on the additional first conductive layer pattern. An additional diffusion preventing layer can be formed pattern on the additional metal ohmic layer pattern. An additional amorphous layer pattern can be formed on the additional diffusion preventing layer pattern and an additional second conductive layer pattern can be formed on the additional amorphous layer pattern. | 07-14-2011 |
Wook-Jae Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100183150 | Shared key management method, shared key generating method and message communication method for scada system, and recording medium - A shared key management method for a Supervisory Control And Data Acquisition (SCADA) system in which a master terminal unit (MTU), a plurality of sub master terminal units (SUB-MTUs), and a plurality of remote terminal units (RTUs) are configured in a sequential hierarchy, is provided. The method includes: (a) at the MTU, generating a plurality of secret keys and respectively allocating the secret keys to the RTUs; (b) at the MTU, generating a group key in a tree structure, wherein a leaf node of the tree structure corresponds to each RTU, a parent node of a node corresponding to an RTU corresponds to a SUB-RTU to which the RTU is connected, a shared key of each node of the group key is generated by hashing shared keys of all child nodes, and a shared key of a leaf node of the group key is set as a secret key of the RTU; (c) at the RTU or the SUM-MTU, receiving and storing shared keys of every node from a node corresponding to itself to a root node; (d) when the RTU or the SUM-MTU is added or deleted, at the MTU, generating shared keys of nodes along a path from a node corresponding to the added or deleted terminal unit to the root node again; and (e) at the RTU or the SUB-MTU, receiving and storing the generated shared keys. According to the key management method for the SCADA system described above, in the case of encrypting and broadcasting or multicasting a message, a computation amount can be reduced. | 07-22-2010 |
Yong-Duck Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100227650 | MOBILE TERMINAL - Disclosed is a mobile terminal including, first and second bodies rotatably coupled to each other, and a driving unit configured to allow a relative rotation of the first and second bodies between a closed configuration and an open configuration, the first and second bodies being overlaid by each other in the closed configuration and rotated away from each other in the open configuration, wherein the driving unit includes rotation motion units connected to each of the first and second bodies and configured to generate the relative rotation, and slide motion units cooperatively operating with the rotation motion unit and configured to relatively slide the first and second bodies with respect to the driving unit between the closed configuration and the open configuration. | 09-09-2010 |
Yong-Won Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090221133 | Methods of Fabricating Silicon on Insulator (SOI) Wafers - Methods of fabricating SOI wafers are provided including providing a donor wafer and forming a hydrogen ion implantation layer in the donor wafer. A circumference portion of one side of the donor wafer is recessed to form a height difference. The one side of the donor wafer and a handle wafer are bonded to form a bonded wafer. The bonded wafer is heat treated to separate the bonded wafer along the hydrogen ion implantation layer. | 09-03-2009 |
Yoo-Seun Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090232946 | EDIBLE PANEL FOR BUILDING A SELF INTERLOCKING MODEL AND SELF INTERLOCKING MODEL KIT COMPRISING THE EDIBLE PANEL - The present invention relates to an edible panel for building a self-interlocking model and a self-interlocking model kit comprising the same edible panel(s), in which the edible panel can be freely molded when it is in a dough state but is transformed into a cookie which is not be deformed or molded after calcining, wherein the edible panels are manufactured into a variety of shapes so that they can be assembled into a variety of models, such as a house model or a ship model, and a user can eat the edible panels after assembling them into a model and baking it, as well as have an experience of assembling the self-interlocking model kit into a self-interlocking model, and appreciating the model assembled by himself or herself using the self-interlocking model kit. The user further can use the self-interlocking model kit comprising the edible panels as celebration gifts. The edible panel for a self-interlocking model kit, according to the present invention has, at least one first coupling projection with a letter “L” shape. | 09-17-2009 |
Young-Jae Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090231170 | APPARATUS AND METHOD FOR DIGITAL FREQUENCY DOWN-CONVERSION - Disclosed is an apparatus and a method for down-converting frequencies of an input signal by separating the signal to which at least two frequencies are allocated according to each frequency, and then outputting at least two digital IF signals in a communication system. The digital down-converting apparatus includes a band-pass filter, an analog-to-digital converter, down-converters, up-converters, and Serializer/Deserializeres, etc. First, the signal to which at least two frequencies are allocated is down-converted into baseband signals respectively. Then, the baseband signals are up-converted into signals of a predetermined frequency respectively. | 09-17-2009 |
Youn Jine Cha, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100225827 | APPARATUS AND METHOD FOR DISPLAYING IMAGE - Provided is an image display apparatus. The apparatus includes a tuner, a demodulator, a demultiplexer, a controller, an OSD controller, a graphic driver, and an OSD displayer. The tuner receives broadcasting signals, the demodulator demodulates signals of a channel selected by the tuner, and the demultiplexer demultiplexes signals demodulated by the demodulator into audio signals, video signals, and a PSIP table. The controller controls information of an electronic program guide extracted from the demultiplexed data to be output in the form of an on-screen-display, and divides the electronic program guide into a text region and a background region to set gradation on the background region of the electronic program guide. The OSD controller performs a gradation process with respect to the background region of the electronic program guide using a gradation value set by the controller. The graphic driver allows the electronic program guide on which the gradation process is performed by the on-screen-display controller to be displayed as an image in the form of the on-screen-display. The on-screen-display displayer displays the on-screen-display representing the electronic program guide delivered from the graphic driver on a screen together with decoded image signals. | 09-09-2010 |