Patent application number | Description | Published |
20090247781 | SYNTHESIS OF PHENOXYACETIC ACID DERIVATIVES - The present invention relates to an improved process for the preparation of substituted 2-(4-carbonylmethoxy-optionally 2,5-disubstituted-phenyl-acetaldehydes, in particular 2-(4-alkoxycarbonylmethoxy-optionally 2,5-disubstituted-phenyl)-acetaldehydes and their use in the synthesis of optionally substituted 2-[4-[2-[[-2-hydroxy-2-(4-hydroxyphenyl)- | 10-01-2009 |
20090306378 | PROCESS FOR PREPARING AMINOCROTONYLAMINO-SUBSTITUTED QUINAZOLINE DERIVATIVES - The invention relates to an improved process for preparing aminocrotonylamino-substituted quinazoline derivatives of general formula (I) wherein the groups R | 12-10-2009 |
20100311985 | INDOLINONE DERIVATIVES AND PROCESS FOR THEIR MANUFACTURE - The present invention relates to specific indolinone derivatives, namely the compounds of formula, in which R | 12-09-2010 |
20110087021 | NOVEL PREPARATION PROCESS - A process for preparing compounds of the formula (I) | 04-14-2011 |
20110201812 | PROCESS FOR THE MANUFACTURE OF AN INDOLINONE DERIVATIVE - The present invention relates to a process for the manufacture of a specific indolinone derivative and a pharmaceutically acceptable salt thereof, namely 3-Z-[1-(4-(N-((4-methyl-piperazin-1-yl)-methylcarbonyl)-N-methyl-amino)-anilino)-1-phenyl-methylene]-6-methoxycarbonyl-2-indolinone and its monoethanesulfonate, to new manufacturing steps and to new intermediates of this process. | 08-18-2011 |
20110207932 | Process for preparing aminocrotonylamino-substituted quinazoline derivatives - The invention relates to an improved process for preparing aminocrotonylamino-substituted quinazoline derivatives of general formula (I) | 08-25-2011 |
Patent application number | Description | Published |
20100164016 | ADJUSTING OF STRAIN CAUSED IN A TRANSISTOR CHANNEL BY SEMICONDUCTOR MATERIAL PROVIDED FOR THRESHOLD ADJUSTMENT - The threshold voltage of a sophisticated transistor may be adjusted by providing a specifically designed semiconductor alloy in the channel region of the transistor, wherein a negative effect of this semiconductor material with respect to inducing a strain component in the channel region may be reduced or over-compensated for by additionally incorporating a strain-adjusting species. For example, a carbon species may be incorporated in the channel region, the threshold voltage of which may be adjusted on the basis of a silicon/germanium alloy of a P-channel transistor. Consequently, sophisticated metal gate electrodes may be formed in an early manufacturing stage. | 07-01-2010 |
20100289094 | ENHANCING DEPOSITION UNIFORMITY OF A CHANNEL SEMICONDUCTOR ALLOY BY AN IN SITU ETCH PROCESS - When forming sophisticated gate electrode structures requiring a threshold adjusting semiconductor alloy for one type of transistor, a recess is formed in the corresponding active region, thereby providing superior process uniformity during the deposition of the semiconductor material. Due to the recess, any exposed sidewall surface areas of the active region may be avoided during the selective epitaxial growth process, thereby significantly contributing to enhanced threshold stability of the resulting transistor including the high-k metal gate stack. | 11-18-2010 |
20100327368 | ENHANCING SELECTIVITY DURING FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY A WET OXIDATION PROCESS - High-k metal gate electrode structures are formed on the basis of a threshold adjusting semiconductor alloy formed in the channel region of one type of transistor, which may be accomplished on the basis of selective epitaxial growth techniques using an oxide hard mask growth mask. The hard mask may be provided with superior thickness uniformity on the basis of a wet oxidation process. Consequently, this may allow re-working substrates prior to the selective epitaxial growth process, for instance in view of queue time violations, while also providing superior transistor characteristics in the transistors that do not require the threshold adjusting semiconductor alloy. | 12-30-2010 |
20110027952 | FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY DEPOSITING A HARD MASK FOR THE SELECTIVE EPITAXIAL GROWTH - A growth mask provided for the deposition of a threshold adjusting semiconductor alloy may be formed on the basis of a deposition process, thereby obtaining superior thickness uniformity. Consequently, P-channel transistors and N-channel transistors with an advanced high-k metal gate stack may be formed with superior uniformity. | 02-03-2011 |
20110129970 | ENHANCING INTERFACE CHARACTERISTICS BETWEEN A CHANNEL SEMICONDUCTOR ALLOY AND A GATE DIELECTRIC BY AN OXIDATION PROCESS - In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material. | 06-02-2011 |
20120164805 | FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY FORMING A HARD MASK LAYER STACK AND APPLYING A PLASMA-BASED MASK PATTERNING PROCESS - When forming sophisticated high-k metal gate electrode structures, a threshold adjusting semiconductor alloy may be formed on the basis of selective epitaxial growth techniques and a hard mask comprising at least two hard mask layers. The hard mask may be patterned on the basis of a plasma-based etch process, thereby providing superior uniformity during the further processing upon depositing the threshold adjusting semiconductor material. In some illustrative embodiments, one hard mask layer is removed prior to actually selectively depositing the threshold adjusting semiconductor material. | 06-28-2012 |
20120282760 | ENHANCING INTERFACE CHARACTERISTICS BETWEEN A CHANNEL SEMICONDUCTOR ALLOY AND A GATE DIELECTRIC BY AN OXIDATION PROCESS - In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material. | 11-08-2012 |
20130113019 | SEMICONDUCTOR DEVICE WITH REDUCED THRESHOLD VARIABILITY HAVING A THRESHOLD ADJUSTING SEMICONDUCTOR ALLOY IN THE DEVICE ACTIVE REGION - Generally, the subject matter disclosed herein is directed to semiconductor devices with reduced threshold variability having a threshold adjusting semiconductor material in the device active region. One illustrative semiconductor device disclosed herein includes an active region in a semiconductor layer of a semiconductor device substrate, the active region having a region length and a region width that are laterally delineated by an isolation structure. The semiconductor device further includes a threshold adjusting semiconductor alloy material layer that is positioned on the active region substantially without overlapping the isolation structure, the threshold adjusting semiconductor alloy material layer having a layer length that is less than the region length. Additionally, the disclosed semiconductor device includes a gate electrode structure that is positioned above the threshold adjusting semiconductor alloy material layer, the gate electrode structure including a high-k dielectric material and a metal-containing electrode material formed above the high-k dielectric material. | 05-09-2013 |
20130299874 | TMAH RECESS FOR SILICON GERMANIUM IN POSITIVE CHANNEL REGION FOR CMOS DEVICE - CMOS devices are enhanced by forming a recess in the positive channel for depositing SiGe. Embodiments include providing a positive channel region and a negative channel region in a silicon substrate for a CMOS device, with an STI region therebetween; removing a native oxide from above the positive channel region to expose a silicon substrate; forming a recess in the silicon substrate in the positive channel region adjacent the STI region; and depositing SiGe in the recess in the positive channel region, where an upper surface of the SiGe is substantially level with an upper surface of the negative channel region. | 11-14-2013 |
20130307090 | ADJUSTING OF STRAIN CAUSED IN A TRANSISTOR CHANNEL BY SEMICONDUCTOR MATERIAL PROVIDED FOR THE THRESHOLD ADJUSTMENT - The threshold voltage of a sophisticated transistor may be adjusted by providing a specifically designed semiconductor alloy in the channel region of the transistor, wherein a negative effect of this semiconductor material with respect to inducing a strain component in the channel region may be reduced or over-compensated for by additionally incorporating a strain-adjusting species. For example, a carbon species may be incorporated in the channel region, the threshold voltage of which may be adjusted on the basis of a silicon/germanium alloy of a P-channel transistor. Consequently, sophisticated metal gate electrodes may be formed in an early manufacturing stage. | 11-21-2013 |
20150076560 | INTEGRATED CIRCUITS INCLUDING EPITAXIALLY GROWN STRAIN-INDUCING FILLS DOPED WITH BORON FOR IMPROVED ROBUSTNESS FROM DELIMINATION AND METHODS FOR FABRICATING THE SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure. An EPI strain-inducing fill is deposited into the cavity. The EPI strain-inducing fill includes a main SiGe layer and a Si cap that overlies the main SiGe layer. The EPI strain-inducing fill is doped with boron and has a first peak boron content in an upper portion of the EPI strain-inducing fill of about 2.5 times or greater than an average boron content in an intermediate portion of the main SiGe layer. | 03-19-2015 |