Patent application number | Description | Published |
20080203470 | Lateral compensation component - A transistor is provided which includes a lateral compensation component. The lateral compensation component includes a plurality of n (or n−) layer/p (or p−) layer pairs, wherein adjacent ones of said pairs are separated by one of an insulator region and/or an intrinsic silicon region. | 08-28-2008 |
20080237701 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING IT - A semiconductor component includes a semiconductor body having an edge with an edge zone of a first conductivity type. Charge compensation regions of a second conductivity type are embedded into the edge zone, with the charge compensation regions extending from a top side of the semiconductor component vertically into the semiconductor body. For the number N | 10-02-2008 |
20090159927 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR ITS PRODUCTION - An integrated circuit device includes a semiconductor body fitted with a first electrode and a second electrode on opposite surfaces. A control electrode on an insulating layer controls channel regions of body zones for a current flow between the two electrodes. A drift section adjoining the channel regions comprises drift zones and charge compensation zones. A part of the charge compensation zones includes conductively connected charge compensation zones electrically connected to the first electrode. Another part includes nearly-floating charge compensation zones, so that an increased control electrode surface has a monolithically integrated additional capacitance C | 06-25-2009 |
20090184373 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device is provided which has a semiconductor substrate. An active cell area having at least one active cell is formed in the semiconductor substrate, wherein at least sections of the active cell area are surrounded by an edge termination region. An integrated gate runner structure is arranged at least partially in the edge termination region and has at least one low electrical resistance portion and at least one high electrical resistance portion which are electrically connected in series with each other. | 07-23-2009 |
20100025748 | SEMICONDUCTOR DEVICE WITH A DYNAMIC GATE-DRAIN CAPACITANCE - A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage. | 02-04-2010 |
20100044788 | SEMICONDUCTOR DEVICE WITH A CHARGE CARRIER COMPENSATION STRUCTURE AND PROCESS - A semiconductor device with a charge carrier compensation structure. In one embodiment, the semiconductor device has a central cell field with a gate and source structure. At least one bond contact area is electrically coupled to the gate structure or the source structure. A capacitance-increasing field plate is electrically coupled to at least one of the near-surface bond contact areas. | 02-25-2010 |
20100181627 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - A semiconductor device and method for manufacturing. One embodiment provides a semiconductor device including an active cell region and a gate pad region. A conductive gate layer is arranged in the active cell region and a conductive resistor layer is arranged in the gate pad region. The resistor layer includes a resistor region which includes a grid-like pattern of openings formed in the resistor layer. A gate pad metallization is arranged at least partially above the resistor layer and in electrical contact with the resistor layer. An electrical connection is formed between the gate layer and the gate pad metallization, wherein the electrical connection includes the resistor region. | 07-22-2010 |
20110241104 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR ITS PRODUCTION - An integrated circuit device includes a semiconductor body fitted with a first electrode and a second electrode on opposite surfaces. A control electrode on an insulating layer controls channel regions of body zones for a current flow between the two electrodes. A drift section adjoining the channel regions comprises drift zones and charge compensation zones. A part of the charge compensation zones includes conductively connected charge compensation zones electrically connected to the first electrode. Another part includes nearly-floating charge compensation zones, so that an increased control electrode surface has a monolithically integrated additional capacitance C | 10-06-2011 |
20110244646 | SEMICONDUCTOR WITH A DYNAMIC GATE-DRAIN CAPACITANCE - A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage. | 10-06-2011 |
20130009227 | SEMICONDUCTOR DEVICE WITH A DYNAMIC GATE-DRAIN CAPACITANCE - A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage. | 01-10-2013 |