| Patent application number | Description | Published |
|---|
| 20080303061 | Substrate Production Method and Substrate - A process for the manufacture of a substrate having a top layer of a first material and an underlying layer of a second material whose lattice parameter is different from that of the first material. The process includes the steps of conducting an amorphization of the top layer to create an amorphous region in the top layer lying between an exposed surface and an amorphization interface, with that portion of the top layer below the interface being shielded from the amorphization and remaining as a crystalline structure; recrystallizing the amorphous region while also creating a network of defects at the interface, wherein the network forms a boundary for dislocations from the crystalline structure of the top layer, and containing the dislocations in the portion of the top layer that is located below the interface. Also, the substrates obtained by the method. | 12-11-2008 |
| 20090014720 | METHOD OF TREATING INTERFACE DEFECTS IN A SUBSTRATE - The present invention relates to a method of treating a structure produced from semiconductor materials, wherein the structure includes a first and second substrates defining a common interface that has defects. The method includes forming a layer, called the disorganized layer, which includes the interface, in which at least a part of the crystal lattice is disorganized; and reorganizing the crystal lattice of the disorganized layer in order to force the defects back deeper into the first substrate. | 01-15-2009 |
| 20090321829 | LOW-COST DOUBLE-STRUCTURE SUBSTRATES AND METHODS FOR THEIR MANUFACTURE - In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-mono-crystalline semi-conducting layer; and top layer disposed on the second insulating layer. Additionally, a first gate electrode can be formed on the top layer and a second gate electrode can be formed in the non-mono-crystalline semi-conducting layer. The invention also provides methods for manufacture of such substrates. | 12-31-2009 |
| 20090321872 | LOW COST SUBSTRATES AND METHOD OF FORMING SUCH SUBSTRATES - In one embodiment, the invention provides engineered substrates having a support with surface pits, an intermediate layer of amorphous material arranged on the surface of the support so as to at least partially fill the surface pits, and a top layer arranged on the intermediate layer. The invention also provides methods for manufacturing the engineered substrates which deposit an intermediate layer on a pitted surface of a support so as to at least partially fill the surface pits, then anneal the intermediate layer, then assemble a donor substrate with the annealed intermediate layer to form an intermediate structure, and finally reduce the thickness of the donor substrate portion of the intermediate structure in order to form the engineered substrate. | 12-31-2009 |
| 20090321873 | LOW-COST SUBSTRATES HAVING HIGH-RESISTIVITY PROPERTIES AND METHODS FOR THEIR MANUFACTURE - In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates. | 12-31-2009 |
| 20100032805 | METHODS AND STRUCTURES FOR RELAXATION OF STRAINED LAYERS - The present invention provides methods for relaxing a strained-material layer and structures produced by the methods. Briefly, the methods include depositing a first low-viscosity layer that includes a first compliant material on the strained-material layer, depositing a second low-viscosity layer that includes a second compliant material on the strained-material layer to form a first sandwiched structure and subjecting the first sandwiched structure to a heat treatment such that the reflow of the first and the second low-viscosity layers permits the strained-material layer to at least partly relax. | 02-11-2010 |
| 20110012200 | SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER - Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 10 | 01-20-2011 |
| 20110042780 | METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES OBTAINED BY SUCH METHODS - In preferred embodiments, this invention provides a semiconductor structure that has a semi-conducting support, an insulating layer arranged on a portion of the support and a semi-conducting superficial layer arranged on the insulating layer. Electronic devices can be formed in the superficial layer and also in the exposed portion of the semi-conducting bulk region of the substrate not covered by the insulating layer. The invention also provides methods of fabricating such semiconductor structures which, starting from a substrate that includes a semi-conducting superficial layer arranged on a continuous insulating layer both of which being arranged on a semi-conducting support, by transforming at least one selected region of a substrate so as to form an exposed semi-conducting bulk region of the substrate. | 02-24-2011 |
| 20110133776 | ARRAYS OF TRANSISTORS WITH BACK CONTROL GATES BURIED BENEATH THE INSULATING FILM OF A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE - This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures. | 06-09-2011 |
| 20110133822 | DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER - This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures. | 06-09-2011 |
| 20110134690 | METHOD OF CONTROLLING A DRAM MEMORY CELL ON THE SeOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER - The invention relates to a method of controlling a DRAM memory cell of an FET transistor on a semiconductor-on-insulator substrate that includes a thin film of semiconductor material separated from a base substrate by an insulating layer or BOX layer, the transistor having a channel and two control gates, a front control gate being arranged on top of the channel and separated from the latter by a gate dielectric and a back control gate being arranged in the base substrate and separated from the channel by the insulating layer (BOX). In a cell programming operation, the front control gate and the back control gate are operated jointly by applying a first voltage to the front control gate and a second voltage to the back control gate, with the first voltage being lower in amplitude than the voltage needed to program the cell when no voltage is applied to the back control gate. | 06-09-2011 |
| 20110134698 | FLASH MEMORY CELL ON SeOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER - The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays. | 06-09-2011 |
| 20110143522 | RELAXATION OF STRAINED LAYERS - The present invention relates to a method for relaxing a strained material layer by depositing a first low-viscosity layer on a first face of a strained-material layer; bonding a first substrate to the first low-viscosity layer to form a first composite structure; subjecting the composite structure to heat treatment sufficient to cause reflow of the first low-viscosity layer so as to at least partly relax the strained-material layer; and applying a mechanical pressure to a second face of the strained material layer which is opposite to the first face. The mechanical pressure is applied perpendicularly to the strained material layer during at least part of the heat treatment. | 06-16-2011 |
