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Carey, NY
Charles F. Carey, Endicott, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20080286886 | Monitoring Cool-Down Stress in a Flip Chip Process Using Monitor Solder Bump Structures - A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip. | 11-20-2008 |
| 20100155943 | SEMICONDUCTOR CHIP USED IN FLIP CHIP PROCESS - A semiconductor chip for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip. | 06-24-2010 |
Jeffrey T. Carey, Victor, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090081885 | DEPOSITION SYSTEM FOR THIN FILM FORMATION - A process for depositing a thin film material on a substrate is disclosed, comprising simultaneously directing a series of gas flows from the output face of a delivery head of a thin film deposition system toward the surface of a substrate, and wherein the series of gas flows comprises at least a first reactive gaseous material, an inert purge gas, and a second reactive gaseous material, wherein the first reactive gaseous material is capable of reacting with a substrate surface treated with the second reactive gaseous material, wherein one or more of the gas flows provides a pressure that at least contributes to the separation of the surface of the substrate from the face of the delivery head. A system capable of carrying out such a process is also disclosed. | 03-26-2009 |
| 20090081886 | SYSTEM FOR THIN FILM DEPOSITION UTILIZING COMPENSATING FORCES - A process for depositing a thin film material on a substrate is disclosed, comprising simultaneously directing a series of gas flows from the output face of a delivery head of a thin film deposition system toward the surface of a substrate, and wherein the series of gas flows comprises at least a first reactive gaseous material, an inert purge gas, and a second reactive gaseous material, wherein the first reactive gaseous material is capable of reacting with a substrate surface treated with the second reactive gaseous material. A system capable of carrying out such a process is also disclosed. | 03-26-2009 |
| 20090217878 | SYSTEM FOR THIN FILM DEPOSITION UTILIZING COMPENSATING FORCES - A process for depositing a thin film material on a substrate is disclosed, comprising simultaneously directing a series of gas flows from the output face of a delivery head of a thin film deposition system toward the surface of a substrate, and wherein the series of gas flows comprises at least a first reactive gaseous material, an inert purge gas, and a second reactive gaseous material, wherein the first reactive gaseous material is capable of reacting with a substrate surface treated with the second reactive gaseous material. A system capable of carrying out such a process is also disclosed. | 09-03-2009 |
| 20090312553 | N-TYPE SEMICONDUCTOR MATERIALS FOR THIN FILM TRANSISTORS - A thin film transistor comprises a layer of organic semiconductor material comprising a tetracarboxylic diimide naphthalene-based compound having, attached to each of the imide nitrogen atoms, an aromatic moiety, at least one of which moieties is substituted with at least one electron donating group. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating an organic thin-film transistor device, preferably by sublimation deposition onto a substrate, wherein the substrate temperature is no more than 100° C. | 12-17-2009 |
Kevin D. Carey, Rensselaer, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090187557 | ARRANGING SEARCH ENGINE RESULTS - Search engine results arranged according to one or more first criteria (e.g., relevancy) are obtained. The results are assigned groups within chosen or calculated relevancy ranges. The results are then resorted within each group according to one or more second criteria (e.g., payment). The groups maintain original placement relative to each other during resorting. A list of at least some of the resorted results is then created for various uses, including search or further manipulation. | 07-23-2009 |
Margaret M. Carey, Waccabuc, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20110161251 | Method and System for Tracking and Budgeting Energy Usage - An energy tracking and reporting system can receive data inputs from multiple sources regarding one or more properties. A central database receives the information and correlates the information for numerous outputs. Information received by the central database can include, for example, property location, property size, property type and property use. Also, occupancy information, energy sources, utilities servicing the property, weather, ISO, environmental guidelines, and the traded or other standard price for the utilities can be stored. The system can calculate a number of factors from the data and return values to the central database. The system can track data trends and store additional information for budgeting, user reporting and certification compliance reporting. Modules can analyze the market rates, calculate efficiency benchmarks, analyze the data stored on the central database and provide the user with multiple tables and charts analyzing all of the factors that tie into energy usage. | 06-30-2011 |
Patrick J. Carey, Endwell, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090144114 | OPERATIONS FOR PRODUCT PROCESSING - An operational process for product distribution includes grouping product into groups when the product is in a first sort level and sorting the groups of product, in a first pass operation, to a second level sort. The method further includes sequencing the second level sort product including late arriving product, in a second pass operation, into a sequence of product. A machine readable code can also be used to implement the functionality of the operational process. | 06-04-2009 |
| 20090145814 | OPERATIONS FOR PRODUCT PROCESSING - An operational process for product distribution includes grouping product into groups when the product is in a first sort level and sorting the groups of product, in a first pass operation, to a second level sort. The method further includes sequencing the second level sort product including late arriving product, in a second pass operation, into a sequence of product. A machine readable code can also be used to implement the functionality of the operational process. | 06-11-2009 |
Sean M. Carey, Hyde Park, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090070719 | Logic Block Timing Estimation Using Conesize - A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time. | 03-12-2009 |
| 20090070720 | System to Identify Timing Differences from Logic Block Changes and Associated Methods - A system to identify timing differences due to logic block changes, the system may include a controller, and storage in communication with the controller. The controller may provide delay values of a previous logic block and a current logic block. The system may also include a timing-modeler to compare the delay values of the previous logic block with the current logic block for timing analysis. The system may further include an interface that provides a report based upon the previous logic block and the current logic block comparison. | 03-12-2009 |
| 20090100394 | Method, Apparatus, and Computer Program Product for Automatically Waiving Non-Compute Indications for a Timing Analysis Process - In the course of unit timing, there exists the possibility for a non-compute (N/C) on a particular net in an IC chip design, which could be caused by numerous things, including but not limited to a pin being tied to power, a floating output, or invalid timing test for a given phase at a test point. A process automatically verifies that all non-computes are understood and exist for valid reasons, in order to ensure all necessary paths are being timed. The process takes a conventional Comprehensive Report output of a unit timing run and generates macro specific N/C reports for designers to review and sign off on. | 04-16-2009 |
Sean Michael Carey, Hyde Park, NY US
| Patent application number | Description | Published |
|---|---|---|
| 20090083569 | Generating a Local Clock Domain Using Dynamic Controls - A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local signal to indicate commencement of the operation and to function as a clock gating signal; latching the clock gating signal to a selected cycle; generating clock domain controls based on the clock gating signal such that the operation times its commencement on the selected cycle; and propagating the clock gating signal in ungated latches for a number of cycles, such that a second operation is restricted from being launched until the operation completes. | 03-26-2009 |
| 20100268522 | MODELING FULL AND HALF CYCLE CLOCK VARIABILITY - A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability. Designers or other entities interpret the results of the shortened STA run data by performing modeling on the output data to generate slack data for design model data paths. STA software executes an STA run with an extended clock cycle to automatically separate half cycle data path (HCDP) slack data from full cycle data path (FCDP) slack data. The full and half cycle clock variability method may automatically adjust slack data for all half cycle data paths (HCDP)s to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation. Designers use a sort of slack data for half cycle data paths (HCDP)s independent of the slack data for the full cycle data path (FCDP)s to modify or otherwise perform design changes to the design model prior to hardware implementation. | 10-21-2010 |