Patent application number | Description | Published |
20130262838 | Memory Disambiguation Hardware To Support Software Binary Translation - A method of memory disambiguation hardware to support software binary translation is provided. This method includes unrolling a set of instructions to be executed within a processor, the set of instructions having a number of memory operations. An original relative order of memory operations is determined. Then, possible reordering problems are detected and identified in software. The reordering problem being when a first memory operation has been reordered prior to and aliases to a second memory operation with respect to the original order of memory operations. The reordering problem is addressed and a relative order of memory operations to the processor is communicated. | 10-03-2013 |
20130275715 | METHOD, APPARATUS, AND SYSTEM FOR EFFICIENTLY HANDLING MULTIPLE VIRTUAL ADDRESS MAPPINGS DURING TRANSACTIONAL EXECUTION - An apparatus and method is described herein for providing structures to support software memory re-ordering within atomic sections of code. Upon a start or end of a critical section, speculative bits of a translation buffer are reset. When a speculative memory access causes an address translation of a virtual address to a physical address, the translation buffer is searched to determine if another entry (a different virtual address) includes the same physical address. And if another entry does include the same physical address, the speculative execution is failed to provide protection from invalid execution resulting from the memory re-ordering. | 10-17-2013 |
20130283249 | INSTRUCTION AND LOGIC TO PERFORM DYNAMIC BINARY TRANSLATION - A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic binary translation. The method may comprise executing original software code compiled targeting a first instruction set, using processor hardware to detect a hot spot in the software code and passing control to a binary translation translator, determining a hot spot region for translation, generating the translated code using a second instruction set, placing the translated code in a translation cache, executing the translated code from the translated cache, and transitioning back to the original software code after the translated code finishes execution. | 10-24-2013 |
20130305019 | Instruction and Logic to Control Transfer in a Partial Binary Translation System - A dynamic optimization of code for a processor-specific dynamic binary translation of hot code pages (e.g., frequently executed code pages) may be provided by a run-time translation layer. A method may be provided to use an instruction look-aside buffer (iTLB) to map original code pages and translated code pages. The method may comprise fetching an instruction from an original code page, determining whether the fetched instruction is a first instruction of a new code page and whether the original code page is deprecated. If both determinations return yes, the method may further comprise fetching a next instruction from a translated code page. If either determinations returns no, the method may further comprise decoding the instruction and fetching the next instruction from the original code page. | 11-14-2013 |
20130311758 | HARDWARE PROFILING MECHANISM TO ENABLE PAGE LEVEL AUTOMATIC BINARY TRANSLATION - A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation. | 11-21-2013 |
20140007066 | STATE RECOVERY METHODS AND APPARTUS FOR COMPUTING PLATFORMS | 01-02-2014 |
20140089271 | MEMORY ADDRESS ALIASING DETECTION - Method and apparatus to efficiently detect violations of data dependency relationships. A memory address associated with a computer instruction may be obtained. A current state of the memory address may be identified. The current state may include whether the memory address is associated with a read or a store instruction, and whether the memory address is associated with a set or a check. A previously accumulated state associated with the memory address may be retrieved from a data structure. The previously accumulated state may include whether the memory address was previously associated with a read or a store instruction, and whether the memory address was previously associated with a set or a check. If a transition from the previously accumulated state to the current state is invalid, a failure condition may be signaled. | 03-27-2014 |
20140095842 | ACCELERATED INTERLANE VECTOR REDUCTION INSTRUCTIONS - A vector reduction instruction is executed by a processor to provide efficient reduction operations on an array of data elements. The processor includes vector registers. Each vector register is divided into a plurality of lanes, and each lane stores the same number of data elements. The processor also includes execution circuitry that receives the vector reduction instruction to reduce the array of data elements stored in a source operand into a result in a destination operand using a reduction operator. Each of the source operand and the destination operand is one of the vector registers. Responsive to the vector reduction instruction, the execution circuitry applies the reduction operator to two of the data elements in each lane, and shifts one or more remaining data elements when there is at least one of the data elements remaining in each lane. | 04-03-2014 |
20140156933 | System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions - Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit. | 06-05-2014 |
20140156978 | Detecting and Filtering Biased Branches in Global Branch History - A processor includes an instruction pipeline for executing instructions including a branching instruction, a counter for counting times that the branching instruction is taken, a register for storing a global branch history as a function of a value of the counter, and a branch prediction unit for predicting branching based on the global branch history. | 06-05-2014 |
20150095625 | OPTIMIZATION OF INSTRUCTIONS TO REDUCE MEMORY ACCESS VIOLATIONS - Mechanisms for reducing memory access violations are disclosed. Sets of instructions may be identified and the identified sets of instructions may be re-translated or optimized to generate other sets of instructions. Execution of the other sets of instructions is analyzed to determine whether additional memory access violations occur. When additional memory access violations occur, further sets of instructions may be generated or re-translation/optimization of instructions may be disabled. | 04-02-2015 |
20150186290 | SYSTEM, APPARATUS, AND METHOD FOR TRANSPARENT PAGE LEVEL INSTRUCTION TRANSLATION - Detailed herein are systems, apparatuses, and methods for transparent page level instruction translation. Exemplary embodiments include an instruction translation lookaside buffer (iTLB), wherein each iTLB entry includes a linear address of a page in memory, a physical address of the page in memory, and a remapping indicator. | 07-02-2015 |
20150186299 | LOAD INSTRUCTION FOR CODE CONVERSION - Embodiments of an invention for a load instruction for code conversion are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction having a source operand to indicate a source location and a destination operand to indicate a destination location. The execution unit is to execute the instruction. Execution of the instruction includes checking the access permissions of the source location and loading content from the source location into the destination location if the access permissions of the source location indicate that the content is executable. | 07-02-2015 |
20150278116 | CONTROL TRANSFER OVERRIDE - Embodiments of an invention for control transfer overrides are disclosed. In one embodiment, a processor includes an instruction unit to receive a control transfer instruction. The instruction unit includes a transfer override register to provide an alternative target for the control transfer instruction. | 10-01-2015 |
20150278516 | RETURN-TARGET RESTRICTIVE RETURN FROM PROCEDURE INSTRUCTIONS, PROCESSORS, METHODS, AND SYSTEMS - A processor includes a decode unit to decode a return target restrictive return from procedure (RTR return) instruction. A return target restriction unit is responsive to the RTR return instruction to determine whether to restrict an attempt by the RTR return instruction to make a control flow transfer to an instruction at a return address corresponding to the RTR return instruction. The determination is based on compatibility of a type of the instruction at the return address with the RTR return instruction and based on compatibility of first return target restrictive information (RTR information) of the RTR return instruction with second RTR information of the instruction at the return address. A control flow transfer unit is responsive to the RTR return instruction to transfer control flow to the instruction at the return address when the return target restriction unit determines not to restrict the attempt. | 10-01-2015 |
20150339109 | STATE RECOVERY METHODS AND APPARATUS FOR COMPUTING PLATFORMS - State recovery methods and apparatus for computing platforms are disclosed. An example method includes inserting a first instruction into optimized code to cause a first portion of a register in a first state to be saved to memory before execution of a region of the optimized code; and maintaining a value indicative of a manner in which a second portion of the register in the first state is to be restored in connection with a state recovery from the optimized code. | 11-26-2015 |
Patent application number | Description | Published |
20110190145 | IN SITU ANALYSIS OF TISSUES - The present invention provides for the simultaneous assessment of a plurality of tissue regions or microregions, the benefit being homogeneity of the sampling, both in terms of tissue content and timing. Discrete regions of a tissue sample, such as those demarcated by microwells formed within the tissue itself or tissue plugs removed from the tissue in a spatially referenced fashion, can be treated with one or more physical or chemical treatments to liberate target molecules of interest. Subsequent analysis of said target molecules by, e.g., mass spectroscopy, permits identification of a variety of biological parameters, including those associated with disease or therapy. | 08-04-2011 |
20140044673 | Classifying Skin Lesions Using Mass Spectrometry Proteomic Approach - The present invention provides for a mass spectrometry proteomic approach to distinguishing Spitz nevi from Spitzoid malignant melanoma. Histology directed mass spectral profiling allows for targeted analysis of sites of melanocytic lesion within formalin-fixed, paraffin embedded excisional biopsies. The classification system identified 5 peptide peaks, of which two have been identified as originating from vimentin and actin. A sensitivity and specificity for Spitz nevi of 97% and 90%, respectively, were achieved. | 02-13-2014 |
20140357526 | HYDROGEL-MEDIATED TISSUE ANALYSIS - A method for analyzing the polypeptide content of animal tissue is described. The method includes the steps of (a) providing an animal tissue specimen; (b) depositing one or more portions of a hydrogel mixture including a protease on spatially discrete portions of the animal tissue specimen; (c) allowing sufficient time to pass for animal tissue under the hydrogel mixture to be form a digested mixture of animal tissue and hydrogel mixture; (d) removing the digested mixture from the animal tissue and extracting the polypeptides from the digested mixture to provide an extract; and (e) analyzing the polypeptide content of the extract by mass spectrometry. | 12-04-2014 |
20150131888 | PREDICTIVE MODELING RELATING MOLECULAR IMAGING MODALITIES - Systems and methods are provided for generating a model relating parameters generated via a first molecular imaging modality to parameters generated via a second molecular imaging modality. First and second feature extractors extract, from images of a region of interest obtained via respective first and second molecular imaging modalities, respective sets of parameters for respective first and second sets of locations. A mapping component associates respective locations of the first and second sets of locations according to their spatial relationship within the region of interest to produce a training set. Each example in the training set comprises a set of parameters associated with a location in the first set of locations and a set of parameters associated with a location in the second set. A modeling component generates a predictive model relating the parameters associated with the first modality with at least one parameter associated with the second modality. | 05-14-2015 |
Patent application number | Description | Published |
20090071834 | Methods and Devices for Concentration and Fractionation of Analytes for Chemical Analysis Including Matrix-Assisted Laser Desorption/Ionization (MALDI) Mass Spectrometry (MS) - A device is described for pre-concentration and purification of analytes from biological samples (such as human serum, plasma, homogenized solid tissue, etc.) to be analyzed by Matrix-Assisted Laser Desorption Ionization Mass Spectrometry (MALDI MS) and methods of use thereof are provided. | 03-19-2009 |
20100133098 | Methods and Devices for Concentration and Purification of Analytes for Chemical Analysis Including Matrix-Assisted Laser Desportion/Ionization (MALDI) Mass Spectrometry (MS) - Analytical methods and devices are disclosed for separating low abundance analytes by electrophoretically driving the analytes through a sieving matrix to first remove high molecular weight species. Subsequently the remaining low abundance analytes are electrophoretically focused onto a capture membrane where the analytes become bound within a small capture site. After this step the capture membrane may be allowed to dry and then attached to a conductive MALDI sample plate. | 06-03-2010 |
20110217783 | CLEAVABLE SURFACTANTS AND METHODS OF USE THEREOF - Cleavable compositions that comprise a polar head, cleavable linker, and a hydrophobic tail; and methods for using them to isolate hydrophobic molecules. | 09-08-2011 |
20160126073 | PATHOLOGY INTERFACE SYSTEM FOR MASS SPECTROMETRY - A diagnostic system and method that includes a non-transitory computer readable medium storing machine executable instructions executable by the processor for altering tissue images, the instructions that further includes an input interface configured to receive a plurality of tissue images, the input interface generating enhanced resolution images from the plurality of tissue images for viewing, an annotation interface for positioning coordinates of interest on the enhanced resolution images, and a matrix model configured to evaluate the coordinates of interest on the enhanced resolutions to generate discrete coordinates, the matrix model using the discrete coordinates in performing mass spectrometer analysis to form at least one viewing image. The system also includes a user interface configured to provide at least one viewing image to a user at the display. | 05-05-2016 |