Patent application number | Description | Published |
20120132268 | ELECTRODE, PHOTOVOLTAIC DEVICE, AND METHOD OF MAKING - In one aspect of the present invention, a transparent electrode, is presented. The transparent electrode includes a substrate and a transparent layer disposed on the substrate. The transparent layer includes (a) a first region including cadmium tin oxide; (b) a second region including tin and oxygen; and (c) a transition region including cadmium, tin, and oxygen interposed between the first region and the second region, wherein an atomic ratio of cadmium to tin in the transition region varies across a thickness of the transition region. The second region further has an electrical resistivity greater than an electrical resistivity of the first region. A photovoltaic device, a photovoltaic module, a method of making is also presented. | 05-31-2012 |
20120164785 | METHOD OF MAKING A TRANSPARENT CONDUCTIVE OXIDE LAYER AND A PHOTOVOLTAIC DEVICE - In one aspect of the present invention, a method is provided. The method includes disposing a substantially amorphous cadmium tin oxide layer on a support; and thermally processing the substantially amorphous cadmium tin oxide layer in an atmosphere substantially free of cadmium from an external source to form a transparent layer, wherein the transparent layer has an electrical resistivity less than about 2×10 | 06-28-2012 |
20130074914 | PHOTOVOLTAIC DEVICES - One aspect of the present invention includes a photovoltaic device. The photovoltaic device includes a window layer disposed on a support and a doped absorber layer disposed on the window layer, wherein the doped absorber layer includes an absorber material and a first metal selected from the group consisting of manganese, cobalt, chromium, zinc, indium, tungsten, molybdenum, and combinations thereof. The photovoltaic devices further includes an interfacial layer disposed on the doped absorber layer, wherein the interfacial comprises a second metal selected from the group consisting of manganese, cobalt, nickel, zinc, and combinations thereof. | 03-28-2013 |
20130078757 | METHODS OF MAKING PHOTOVOLTAIC DEVICES - One aspect of the present invention includes a method of making a photovoltaic device. The method includes disposing an absorber layer on a window layer. The method further includes treating at least a portion of the absorber layer with a first solution including a first metal salt to form a first component, wherein the first metal salt comprises a first metal selected from the group consisting of manganese, cobalt, chromium, zinc, indium, tungsten, molybdenum, and combinations thereof. The method further includes treating at least a portion of the first component with cadmium chloride to form a second component. The method further includes treating at least a portion of the second component with a second solution including a second metal salt to form an interfacial layer on the second component, wherein the second metal salt comprises a second metal selected from the group consisting of manganese, cobalt, nickel, zinc, and combinations thereof. | 03-28-2013 |
20130109124 | METHODS OF MAKING A TRANSPARENT LAYER AND A PHOTOVOLTAIC DEVICE | 05-02-2013 |
20140060635 | PHOTOVOLTAIC DEVICES - Photovoltaic devices are presented. A photovoltaic device includes a window layer and a semiconductor layer including a semiconductor material disposed on window layer. The semiconductor layer includes a first region and a second region, the first region disposed proximate to the window layer, and the second region including a chalcogen-rich region, wherein the first region and the second region include a dopant, and an average atomic concentration of the dopant in the second region is greater than an average atomic concentration of the dopant in the first region. | 03-06-2014 |
20140065763 | METHODS OF TREATING A SEMICONDUCTOR LAYER - Methods for treating a semiconductor layer including a semiconductor material are presented. A method includes contacting at least a portion of the semiconductor material with a passivating agent. The method further includes forming a first region in the semiconductor layer by introducing a dopant into the semiconductor material; and forming a chalcogen-rich region. The method further includes forming a second region in the semiconductor layer, the second region including a dopant, wherein an average atomic concentration of the dopant in the second region is greater than an average atomic concentration of the dopant in the first region. Photovoltaic devices are also presented. | 03-06-2014 |
20140220727 | Methods of Making Photovoltaic Devices - A method of making a photovoltaic device is presented. The method includes disposing an absorber layer on a window layer. The method further includes treating at least a portion of the absorber layer with a first solution including a first metal salt to form a first component, wherein the first metal salt comprises a first metal selected from the group consisting of manganese, cobalt, chromium, zinc, indium, tungsten, molybdenum, and combinations thereof. The method further includes treating at least a portion of the first component with cadmium chloride to form a second component. The method further includes treating at least a portion of the second component with a second solution including a second metal salt to form an interfacial layer on the second component, wherein the second metal salt comprises a second metal selected from the group consisting of manganese, cobalt, nickel, zinc, and combinations thereof. | 08-07-2014 |
Patent application number | Description | Published |
20140256141 | METHODS FOR FABRICATING INTEGRATED CIRCUITS UTILIZING SILICON NITRIDE LAYERS - A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles. | 09-11-2014 |
20140346648 | LOW-K NITRIDE FILM AND METHOD OF MAKING - A low-K nitride film and a method of making are disclosed. Embodiments include forming a nitride film on a substrate by plasma enhanced chemical vapor deposition (PECVD) and periodically fluctuating a production of radicals during the PECVD based, at least in part, on plural cycles of a radiofrequency (RF) induced plasma. | 11-27-2014 |
20150104948 | FACILITATING ETCH PROCESSING OF A THIN FILM VIA PARTIAL IMPLANTATION THEREOF - Methods of facilitating fabrication of circuit structures are provided which include, for instance: providing a structure with a film layer; modifying an etch property of the film layer by implanting at least one species of element or molecule into the upper portion of the film layer, the etch property of the film layer remaining unmodified beneath the upper portion; and subjecting the structure and film layer with the modified etch property to an etching process, the modified etch property of the film layer facilitating the etching process. Modifying the etch property of the upper portion of the film layer may include making the upper portion of the film layer preferentially susceptible or preferentially resistant to the etching process depending on the circuit fabrication approach being facilitated. | 04-16-2015 |
20150194342 | FORMATION OF CARBON-RICH CONTACT LINER MATERIAL - Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material including a carbon-containing species and an elemental carbon disposed therein, the carbon-containing species and the elemental carbon together defining a set carbon content within the carbon-rich contact liner material; and depositing the carbon-rich contact liner material conformally within the at least one contact opening disposed over the semiconductor substrate. | 07-09-2015 |
20150357285 | FORMATION OF CARBON-RICH CONTACT LINER MATERIAL - Conductive contact structure of a circuit structures and methods of fabrication thereof are provided. The fabrication includes, for instance, providing at least one contact opening disposed over a semiconductor substrate; forming a carbon-rich contact liner material having a set carbon content conformally within the at least one contact opening disposed over the semiconductor substrate. | 12-10-2015 |
Patent application number | Description | Published |
20130157405 | MANUFACTURING METHODS FOR SEMICONDUCTOR DEVICES - A method of manufacturing semiconductor assemblies is provided. The manufacturing method includes thermally processing a first semiconductor assembly comprising a first semiconductor layer disposed on a first support and thermally processing a second semiconductor assembly comprising a second semiconductor layer disposed on a second support. The first and second semiconductor assemblies are thermally processed simultaneously, and the first and second semiconductor assemblies are arranged such that the first semiconductor layer faces the second semiconductor layer during the thermal processing. | 06-20-2013 |
20130192667 | PHOTOVOLTAIC DEVICES AND METHOD OF MAKING - A photovoltaic device is presented. The photovoltaic device includes a transparent conductive layer; a window layer disposed on the transparent conductive layer; and an absorber layer disposed on the window layer. The window layer includes a low-diffusivity layer disposed adjacent to the transparent conductive layer and a high-diffusivity layer interposed between the low-diffusivity layer and the absorber layer. Method of making a photovoltaic device is also presented. | 08-01-2013 |
20130337600 | METHOD OF PROCESSING A SEMICONDUCTOR ASSEMBLY - A method for processing a semiconductor assembly is presented. The method includes thermally processing a semiconductor assembly in a non-oxidizing atmosphere at a pressure greater than about 10 Torr. The semiconductor assembly includes a semiconductor layer disposed on a support, and the semiconductor layer includes cadmium and sulfur. | 12-19-2013 |
20140000673 | PHOTOVOLTAIC DEVICE AND METHOD OF MAKING | 01-02-2014 |
20140004655 | MANUFACTURING METHODS FOR SEMICONDUCTOR DEVICES | 01-02-2014 |
20140060608 | PHOTOVOLTAIC DEVICE AND METHOD OF MAKING - A photovoltaic device is presented. The device includes an intermediate layer disposed between an absorber layer and a back contact layer. The intermediate layer includes a metal or metalloid of Group 15 and oxygen. Method for making a photovoltaic device is also presented. | 03-06-2014 |
20140170801 | METHODS OF FABRICATING A PHOTOVOLTAIC MODULE, AND RELATED SYSTEM - A method of processing a semiconductor assembly is presented. The method includes fabricating a photovoltaic module including a semiconductor assembly. The fabrication step includes performing an efficiency enhancement treatment on the semiconductor assembly, wherein the efficiency enhancement treatment includes light soaking the semiconductor assembly, and heating the semiconductor assembly. The semiconductor assembly includes a window layer having an average thickness less than about 80 nanometers, wherein the window layer includes cadmium and sulfur. A related system is also presented. | 06-19-2014 |
20140246083 | PHOTOVOLTAIC DEVICES AND METHOD OF MAKING - A photovoltaic device is presented. The photovoltaic device includes a buffer layer disposed on a transparent conductive oxide layer; a window layer disposed on the buffer layer; and an interlayer interposed between the transparent conductive oxide layer and the window layer. The interlayer includes a metal species, wherein the metal species includes gadolinium, beryllium, calcium, barium, strontium, scandium, yttrium, hafnium, cerium, lutetium, lanthanum, or combinations thereof. A method of making a photovoltaic device is also presented | 09-04-2014 |
Patent application number | Description | Published |
20130126830 | TRANSISTOR EMPLOYING VERTICALLY STACKED SELF-ALIGNED CARBON NANOTUBES - A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel. | 05-23-2013 |
20130130446 | TRANSISTOR EMPLOYING VERTICALLY STACKED SELF-ALIGNED CARBON NANOTUBES - A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel. | 05-23-2013 |
20140000712 | NIOBIUM THIN FILM STRESS RELIEVING LAYER FOR THIN-FILM SOLAR CELLS | 01-02-2014 |
20140042392 | DOUBLE CONTACTS FOR CARBON NANOTUBES THIN FILM DEVICES - A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled. | 02-13-2014 |
20140045333 | DOUBLE CONTACTS FOR CARBON NANOTUBES THIN FILM DEVICES - A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled. | 02-13-2014 |
20140117498 | Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process - In one aspect, a memory cell capacitor is provided. The memory cell capacitor includes a silicon wafer; at least one trench in the silicon wafer; a silicide within the trench that serves as a bottom electrode of the memory cell capacitor, wherein a contact resistance between the bottom electrode and the silicon wafer is from about 1×10 | 05-01-2014 |
20140120687 | Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process - In one aspect, a method of fabricating a memory cell capacitor includes the following steps. At least one trench is formed in a silicon wafer. A thin layer of metal is deposited onto the silicon wafer, lining the trench, using a conformal deposition process under conditions sufficient to cause at least a portion of the metal to self-diffuse into portions of the silicon wafer exposed within the trench forming a metal-semiconductor alloy. The metal is removed from the silicon wafer selective to the metal-semiconductor alloy such that the metal-semiconductor alloy remains. The silicon wafer is annealed to react the metal-semiconductor alloy with the silicon wafer to form a silicide, wherein the silicide serves as a bottom electrode of the memory cell capacitor. A dielectric is deposited into the trench covering the bottom electrode. A top electrode is formed in the trench separated from the bottom electrode by the dielectric. | 05-01-2014 |
20140147675 | STRUCTURE AND METHOD FOR A GRAPHENE-BASED APPARATUS - An approach is provided for a structure and a method for a graphene-based apparatus. The method comprises acts of forming a graphene layer on a metal layer; forming a protective layer on the graphene layer that makes the graphene layer disposed between the metal layer and the protective layer; transferring the protective layer with the graphene layer and the metal layer onto a substrate; removing the metal layer off from the graphene layer; and forming a conducting layer on the graphene layer. Accordingly, the proposed structure of the graphene-based apparatus is able to prevent graphene damage during the transferring, and because of he use of the protective layer in the structure, the roller can be used to apply the stress which enables roll-to-roll type process and significantly improves the manufacturing throughput. | 05-29-2014 |
20140203360 | REDUCING CONTACT RESISTANCE BY DIRECT SELF-ASSEMBLING - As stated above, methods of forming a source/drain contact for a transistor are disclosed. In one embodiment, a transistor is formed on a semiconductor-on-insulator (SOI) substrate, which includes a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate. This forming can include forming a gate and a source/drain region. A hardmask can then be formed over the transistor and a self-assembling (DSA) polymer can be directed to cover a portion of the source/drain region. A set of trenches can be formed through the hardmask and into the source/drain region using the DSA polymer as a mask. Then the polymer and the hardmask can be stripped, leaving the trenched source/drain region. | 07-24-2014 |
20140264482 | CARBON-DOPED CAP FOR A RAISED ACTIVE SEMICONDUCTOR REGION - After formation of a disposable gate structure, a raised active semiconductor region includes a vertical stack, from bottom to top, of an electrical-dopant-doped semiconductor material portion and a carbon-doped semiconductor material portion. A planarization dielectric layer is deposited over the raised active semiconductor region, and the disposable gate structure is replaced with a replacement gate structure. A contact via cavity is formed through the planarization dielectric material layer by an anisotropic etch process that employs a fluorocarbon gas as an etchant. The carbon in the carbon-doped semiconductor material portion retards the anisotropic etch process, and the carbon-doped semiconductor material portion functions as a stopping layer for the anisotropic etch process, thereby making the depth of the contact via cavity less dependent on variations on the thickness of the planarization dielectric layer or pattern factors. | 09-18-2014 |
20140273449 | MAGNETIC TRAP FOR CYLINDRICAL DIAMAGNETIC MATERIALS - A system for self-aligning diamagnetic materials includes first and second magnets contacting each other along a contact line and having a diametric magnetization perpendicular to the contact line and a diamagnetic rod positioned to levitate above the contact line of the first and second magnets. | 09-18-2014 |
20140273450 | MAGNETIC TRAP FOR CYLINDRICAL DIAMAGNETIC MATERIALS - A method of arranging a diamagnetic rod includes levitating a diamagnetic rod above a contact line at which a first magnet contacts a second magnet, the first magnet and the second magnet having diametric magnetization in a direction perpendicular to the contact line. | 09-18-2014 |
20140312249 | COLORIMETRIC RADIATION DOSIMETRY BASED ON FUNCTIONAL POLYMER AND NANOPARTICLE HYBRID - A method for colorimetric radiation dosimetry includes subjecting an aggregate including a polymeric matrix having uniformly dispersed nanoparticles therein to radiation. The aggregate is soaked in a solution selected to dissolve decomposed pieces of the polymeric matrix to release into the solution nanoparticles from the decomposed pieces. Color of the solution is compared to a reference to determine a dose of radiation based on number of liberated nanoparticles. | 10-23-2014 |
20140315316 | COLORIMETRIC RADIATION DOSIMETRY BASED ON FUNCTIONAL POLYMER AND NANOPARTICLE HYBRID - A method for colorimetric radiation dosimetry includes subjecting an aggregate including a polymeric matrix having uniformly dispersed nanoparticles therein to radiation. The aggregate is soaked in a solution selected to dissolve decomposed pieces of the polymeric matrix to release into the solution nanoparticles from the decomposed pieces. Color of the solution is compared to a reference to determine a dose of radiation based on number of liberated nanoparticles. | 10-23-2014 |
20140326047 | Techniques for Fabricating Janus Sensors - Electromechanical sensors that employ Janus micro/nano-components and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating an electromechanical sensor includes the following steps. A back gate is formed on a substrate. A gate dielectric is deposited over the back gate. An intermediate layer is formed on the back gate having a micro-fluidic channel formed therein. Top electrodes are formed above the micro-fluidic channel. One or more Janus components are placed in the micro-fluidic channel, wherein each of the Janus components has a first portion having an electrically conductive material and a second portion having an electrically insulating material. The micro-fluidic channel is filled with a fluid. The electrically insulating material has a negative surface charge at a pH of the fluid and an isoelectric point at a pH less than the pH of the fluid. | 11-06-2014 |
20140326613 | Techniques for Fabricating Janus Sensors - Electromechanical sensors that employ Janus micro/nano-components and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating an electromechanical sensor includes the following steps. A back gate is formed on a substrate. A gate dielectric is deposited over the back gate. An intermediate layer is formed on the back gate having a micro-fluidic channel formed therein. Top electrodes are formed above the micro-fluidic channel. One or more Janus components are placed in the micro-fluidic channel, wherein each of the Janus components has a first portion having an electrically conductive material and a second portion having an electrically insulating material. The micro-fluidic channel is filled with a fluid. The electrically insulating material has a negative surface charge at a pH of the fluid and an isoelectric point at a pH less than the pH of the fluid. | 11-06-2014 |
20140345687 | NIOBIUM THIN FILM STRESS RELIEVING LAYER FOR THIN-FILM SOLAR CELLS - A photovoltaic device includes a thermal stress relieving layer on top of a substrate; a back ohmic contact on the thermal stress relieving layer; and a p-type semiconductor photon absorber layer on the back ohmic contact. The back ohmic contact comprises a metallic compound of the sacrificial back electrode metal layer and the absorber layer, in combination with the thermal stress relieving layer. The thermal stress relieving layer has a substantially similar thermal expansion coefficient with respect to the substrate and the absorber layer and a lower Young's modulus with respect to the sacrificial back electrode metal layer. | 11-27-2014 |
20140353589 | REPLACEMENT GATE SELF-ALIGNED CARBON NANOSTRUCTURE TRANSISTOR - A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal. | 12-04-2014 |
20140353590 | REPLACEMENT GATE SELF-ALIGNED CARBON NANOSTRUCTURE TRANSISTOR - A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal. | 12-04-2014 |
20150014755 | JANUS COMPLEMENTARY MEMS TRANSISTORS AND CIRCUITS - A method of fabricating an electromechanical device includes the following steps. A first and a second back gate are formed over a substrate. An etch stop layer is formed covering the first and second back gates. Electrodes are formed over the first and second back gates, wherein the electrodes include one or more gate, source, and drain electrodes, wherein gaps are present between the source and drain electrodes. One or more Janus components are placed the gaps, each of which includes a first portion having an electrically conductive material and a second portion having an electrically insulating material, and wherein i) the first or second portion of the Janus components placed in a first one of the gaps has a fixed positive surface charge and ii) the first or second portion of the Janus components placed in a second one of the gaps has a fixed negative surface charge. | 01-15-2015 |
20150064806 | MAGNETIC TRAP FOR CYLINDRICAL DIAMAGNETIC MATERIALS - A system for self-aligning diamagnetic materials includes first and second magnets contacting each other along a contact line and having a diametric magnetization perpendicular to the contact line and a diamagnetic rod positioned to levitate above the contact line of the first and second magnets. | 03-05-2015 |
20150285920 | COLORIMETRIC RADIATION DOSIMETRY BASED ON FUNCTIONAL POLYMER AND NANOPARTICLE HYBRID - A method for colorimetric radiation dosimetry includes subjecting an aggregate including a polymeric matrix having uniformly dispersed nanoparticles therein to radiation. The aggregate is soaked in a solution selected to dissolve decomposed pieces of the polymeric matrix to release into the solution nanoparticles from the decomposed pieces. Color of the solution is compared to a reference to determine a dose of radiation based on number of liberated nanoparticles. | 10-08-2015 |
20150287633 | MAGNETIC TRAP FOR CYLINDRICAL DIAMAGNETIC MATERIALS - A system for self-aligning diamagnetic materials includes first and second magnets contacting each other along a contact line and having a diametric magnetization perpendicular to the contact line and a diamagnetic rod positioned to levitate above the contact line of the first and second magnets. | 10-08-2015 |
20150287942 | FORMING PN JUNCTION CONTACTS BY DIFFERENT DIELECTRICS - A carbon nanotube transistor and method of manufacturing a carbon nanotube transistor is disclosed. The carbon nanotube transistor includes a carbon nanotube on a substrate, a gate electrode deposited on the carbon nanotube, and at least one of a source electrode and a drain electrode deposited on the carbon nanotube and separated from the gate electrode by a space region. The carbon nanotube is doped at the gate electrode an in the space region to form a p-n junction. | 10-08-2015 |
20150311457 | FORMING PN JUNCTION CONTACTS BY DIFFERENT DIELECTRICS - A carbon nanotube transistor and method of manufacturing a carbon nanotube transistor is disclosed. The carbon nanotube transistor includes a carbon nanotube on a substrate, a gate electrode deposited on the carbon nanotube, and at least one of a source electrode and a drain electrode deposited on the carbon nanotube and separated from the gate electrode by a space region. The carbon nanotube is doped at the gate electrode an in the space region to form a p-n junction. | 10-29-2015 |
20160005646 | MAGNETIC TRAP FOR CYLINDRICAL DIAMAGNETIC MATERIALS - A method for self-aligning diamagnetic materials includes contacting first and second magnets together other along a contact line so as to generate a diametric magnetization that is perpendicular to the contact line. A diamagnetic rod is positioned with respect to the first and second magnets to levitate above the contact line of the first and second magnets. | 01-07-2016 |
20160093819 | FRINGING FIELD ASSISTED DIELECTROPHORESIS ASSEMBLY OF CARBON NANOTUBES - A method of arranging at least one carbon nanotube on a semiconductor substrate includes depositing the at least one carbon nanotube on a dielectric layer of the semiconductor device. The method further includes arranging the at least one carbon nanotube on the dielectric layer in response to applying a voltage potential to an electrically conductive electrode of the semiconductor device, and applying a ground potential to an electrically conductive semiconductor layer of the semiconductor device. | 03-31-2016 |