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Byung Yoon
Byung Yoon Ahn, Sanin-Myeon Haman-Gun KR
| Patent application number | Description | Published |
|---|---|---|
| 20100036065 | Maleimide-alpha-alkylstyrene-based tetrapolymer with low molten viscosity and continuous bulk process for producing it - Disclosed are a maleimide-α-alkylstyrene-based, heat-resistant bulk tetrapolymer and a preparation process thereof. More specifically, disclosed are a bulk tetrapolymer, comprising 5-60 wt % of an N-substituted maleimide monomer, 10-70 wt % of an α-alkylstyrene monomer, 5-50 wt % of an unsaturated nitrile monomer and 3-50 wt % of an aromatic vinyl monomer, as well as a continuous bulk polymerization process for preparing the same. The disclosed bulk tetrapolymer has a weight-average molecular weight (Mw) of 70,000-300,000 and a glass transition temperature of 150-200° C., shows excellent high-temperature thermal stability and heat resistance and a remarkably low melt viscosity, and thus is excellent not only in processability, but also in productivity, processability, moldability and blendability, when it is blended with other resins. Also, the continuous bulk polymerization process is equipped with a devolatilizer and enables the bulk tetrapolymer to be produced at low cost and high efficiency. | 02-11-2010 |
Byung Yoon Choi, Seoul-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090024843 | COMPUTER HAVING FLASH MEMORY AND METHOD OF OPERATING FLASH MEMORY - Provided is a method of variably establishing storage areas of a flash memory according to the status of a system in a computer having flash memory in which booting data and execution data are stored. The computer includes: a flash memory including a storage area that is divided into a boot area for storing booting data and a cache area for storing execution data, and supplementing a reading speed of a main storage device; a flash controller designating a location to which the data stored in the flash memory is written; and a main controller calculating an area ratio of the flash memory according to the operating status of a PC, controlling the flash controller, and reestablishing the area ratio between the boot area and the cache area. | 01-22-2009 |
Byung Yoon Kang, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090095811 | METHODS FOR CONTROLLING ACCESS TO DATA STORED IN SMART CARDS AND RELATED DEVICES - In a method for controlling access to data stored on a smart card, an external request for communication with the smart card is received via a first communication interface. The external request for communication may be a request for communication over a second communication interface, for example, from a smart card reader. Private data from the smart card is transmitted via the second communication interface responsive to authentication of a user of the smart card. Related devices are also discussed. | 04-16-2009 |
| 20090136753 | METHOD FOR MANUFACTURING OPTICAL FIBER PREFORM, OPTICAL FIBER PREFORM AND OPTICAL FIBER MANUFACTURED USING THE SAME - The present invention relates to a method for manufacturing an optical fiber preform using an MCVD process comprising (A) forming a predetermined thickness of a cladding layer in a preform tube by repeating a unit process of heating an outer peripheral surface of the preform tube at 1,700 to 2,5000 C using a heat source moving in a process direction, and simultaneously injecting cladding layer forming gas and chlorine (Cl) gas into the preform tube; and (B) forming a predetermined thickness of a core layer in the preform tube by repeating a unit process of heating the outer peripheral surface of the preform tube at 1,700 to 2,5000 C using the heat source moving in a process direction, and simultaneously injecting core layer forming gas and chlorine (Cl) gas into the preform tube having the cladding layer. | 05-28-2009 |
| 20090177819 | INTEGRATED CIRCUIT CARDS INCLUDING MULTIPLE COMMUNICATION INTERFACES AND RELATED METHODS OF OPERATION - A multi-interface integrated circuit (IC) card includes a first communication interface configured to communicate with a host device in a first protocol mode, a second communication interface configured to communicate with the host device in a second protocol mode different than the first protocol mode, and a controller configured to detect a voltage supplied by the host device and a counter value associated therewith. The controller is configured to enable either the first interface or the second interface according to the detected voltage and the counter value. Related methods of operation are also discussed. | 07-09-2009 |
Byung Yoon Kang, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090049326 | CLOCK SIGNAL GENERATOR FOR GENERATING STABLE CLOCK SIGNAL, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHODS OF OPERATING - A clock signal generator can include a clock signal generation unit that is configured to generate a clock signal. A clock signal control unit is configured to count a number of pulses of the clock signal during a reference time, and to compare the number of pulses with a reference value to provide a comparison result, and to generate a control signal based on the comparison result, where the clock signal generation unit increases or decreases the number of pulses of the clock signal based on the control signal. | 02-19-2009 |