| Patent application number | Description | Published |
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| 20080220556 | METHOD OF MANUFACTURING ENHANCEMENT TYPE SEMICONDUCTOR PROBE AND INFORMATION STORAGE DEVICE HAVING THE SEMICONDUCTOR PROBE USING THE SAME - A method of manufacturing an enhancement type semiconductor probe and an information storage device having the enhancement type semiconductor probe are provided. The method involves using an anisotropic wet etching and a side-wall in which influence of process parameters upon the performance of a device is reduced to improve reliability of the device in mass-production, and factors of degrading measuring sensitivity is removed to improve the performance of the device. | 09-11-2008 |
| 20080272426 | Nonvolatile Memory Transistors Including Active Pillars and Related Methods and Arrays - Nonvolatile memory transistors including active pillars having smooth side surfaces with an acute inward angle are provided. The transistor has an active pillar having smooth side surfaces with an acute inward angle and protrudes from semiconductor substrate. A gate electrode surrounds the side surfaces of the active pillar. A charge storage layer is provided between the active pillar and the gate electrode. Nonvolatile memory arrays including the transistor and related methods of fabrication are also provided. | 11-06-2008 |
| 20080296659 | Nand Flash Memory Array Having Pillar Structure and Fabricating Method of the Same - The present invention relates to a NAND flash memory array having vertical channels and sidewall gate structure and a fabricating method of the same. A NAND flash memory array of the present invention has insulator strip structure and one or more semiconductor strips are next to the both sides of the insulator strip. A NAND flash memory array of the present invention allows for an improvement of the integrity by decreasing the memory cell area by half and less, and solves the problems of the conventional three-dimensional structure regarding isolation between not only channels but also source/drain regions at the bottom of trenches. A method for fabricating the NAND flash memory array having a pillar structure, which uses the conventional CMOS process and an etching process with minimum masks, enables to cut down costs. | 12-04-2008 |
| 20090207667 | NAND FLASH MEMORY ARRAY WITH CUT-OFF GATE LINE AND METHODS FOR OPERATING AND FABRICATING THE SAME - A NAND flash memory array, an operating method and a fabricating method of the same are provided. The NAND flash memory array has a cut-off gate line under a control gate in order to operate two cells having vertical channels independently with one control gate (i.e., a shared word line). The memory cell area is reduced considerably compared to the conventional vertical channel structure, and is better for high integration. A shared cut-off gate turn off is made during a programming operation and prevents programming the opposite cell by a self-boosting effect. It is possible to shield electrically with a shared word line (a control gate) during a reading operation, and minimizes the effect of storage condition of the opposite cell. Also, the NAND flash memory array can be fabricated by using the conventional CMOS process. | 08-20-2009 |
| 20090239345 | Methods of Fabricating Nonvolatile Semiconductor Memory Devices - A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines. | 09-24-2009 |
| 20090242965 | MEMORY CELL DEVICE HAVING VERTICAL CHANNEL AND DOUBLE GATE STRUCTURE - A memory cell device having a vertical channel and a double gate structure is provided. More specifically, a memory cell device having a vertical channel and a double gate structure is characterized by having a pillar active region with a predetermined height, which is including a first semiconductor layer forming a first source/drain region, a second semiconductor layer being placed under the first semiconductor layer with a predetermined distance and forming a second source/drain region, and a third semiconductor layer forming a body region and a channel region between the first semiconductor layer and the second semiconductor layer, and therefore, there is no need for unnecessary contacts when it is used as a unit cell for any type of memory array, not to speak of NOR type flash memory array. And the present invention makes to program/erase more effectively and increase the read speed and the amount of sensing current. | 10-01-2009 |
| 20100001339 | Semiconductor device and methods of forming and operating the same - Provided are a semiconductor device and a methods of forming and operating the semiconductor device. The semiconductor device may include active pillars extending from a semiconductor substrate and disposed two dimensionally disposed on the semiconductor substrate, upper interconnections connecting the active pillars along one direction, lower interconnections crossing the upper interconnections and disposed between the active pillars, word lines crossing the upper interconnections and disposed between the active pillars, and data storage patterns disposed between the word lines and the active pillars. | 01-07-2010 |
| 20100015773 | SONOS MEMORY DEVICE HAVING CURVED SURFACE AND METHOD FOR FABRICATING THE SAME - A new SONOS memory device is provided, in which a conventional planar surface of multi-dielectric layers (ONO layers) is instead formed with a curved surface such as a cylindrical shape, and included is a method for fabricating the same. | 01-21-2010 |
| 20110163371 | METHODS OF FABRICATING NONVOLATILE SEMICONDUCTOR MEMORY DEVICES - A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines. | 07-07-2011 |
