| Patent application number | Description | Published |
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| 20090261389 | COMPOSITION FOR OXIDE SEMICONDUCTOR THIN FILM, FIELD EFFECT TRANSISTOR USING THE COMPOSITION, AND METHOD OF FABRICATING THE TRANSISTOR - A composition for an oxide semiconductor thin film, a field effect transistor (FET) using the composition, and a method of fabricating the FET are provided. The composition includes an aluminum oxide, a zinc oxide, and a tin oxide. The thin film formed of the composition remains in amorphous phase at a temperature of 400° C or less. The FET using an active layer formed of the composition has improved electrical characteristics and can be fabricated using a low-temperature process without expensive raw materials, such as In and Ga. | 10-22-2009 |
| 20100006837 | COMPOSITION FOR OXIDE SEMICONDUCTOR THIN FILM, FIELD EFFECT TRANSISTOR USING THE COMPOSITION AND METHOD OF FABRICATING THE TRANSISTOR - Provided are a composition for an oxide semiconductor thin film, a field effect transistor using the same and a method of fabricating the field effect transistor. The composition includes an aluminum oxide, a zinc oxide, an indium oxide and a tin oxide. The thin film formed of the composition is in amorphous phase. The field effect transistor having an active layer formed of the composition can have an improved electrical characteristic and be fabricated by a low temperature process. | 01-14-2010 |
| 20100155792 | TRANSPARENT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - Provided is a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. Here, the lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel. Thus, the use of the multi-layered transparent conductive layer can ensure transparency and conductivity, overcome a problem of contact resistance between the source and drain electrodes and a semiconductor, and improve processibility by patterning the multi-layered transparent conductive layer all at once, while deposition is performed layer by layer. | 06-24-2010 |
| 20100243994 | TRANSPARENT NONVOLATILE MEMORY THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - Provided are a transparent nonvolatile memory thin film transistor (TFT) and a method of manufacturing the same. The memory TFT includes source and drain electrodes disposed on a transparent substrate. A transparent semiconductor thin layer is disposed on the source and drain electrodes and the transparent substrate interposed between the source and drain electrodes. An organic ferroelectric thin layer is disposed on the transparent semiconductor thin layer. A gate electrode is disposed on the organic ferroelectric thin layer in alignment with the transparent semiconductor thin layer. Thus, the transparent nonvolatile memory TFT employs the organic ferroelectric thin layer, the oxide semiconductor thin layer, and auxiliary insulating layers disposed above and below the organic ferroelectric thin layer, thereby enabling low-cost manufacture of a transparent nonvolatile memory device capable of a low-temperature process. | 09-30-2010 |
| 20110049592 | NONVOLATILE MEMORY CELL AND METHOD OF MANUFACTURING THE SAME - Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region. | 03-03-2011 |
| 20110095702 | STACKED ORGANIC LIGHT-EMITTING DEVICE - A stacked organic light-emitting device is provided. The stacked organic light-emitting device includes a first electrode, first and second light-emitting units formed under and on the first electrode respectively, transparent or semi-transparent second and third electrodes formed under the first light-emitting unit and on the second light-emitting unit respectively, and having the same polarity, and a drive controller electrically connected with the first, second and third electrodes to connect the first and second light-emitting units in parallel, and capable of controlling at least one of the first and second light-emitting units to emit light. Accordingly, the organic light-emitting device has a lower driving voltage than a conventional stacked light-emitting device in which light-emitting units are serially connected. | 04-28-2011 |
| 20110253997 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device using a p-type oxide semiconductor layer and a method of manufacturing the same. The device includes the p-type oxide layer formed of at least one oxide selected from the group consisting of a copper(Cu)-containing copper monoxide, a tin(Sn)-containing tin monoxide, a copper tin oxide containing a Cu—Sn alloy, and a nickel tin oxide containing a Ni—Sn alloy. Thus, transparent or opaque devices are easily developed using the p-type oxide layer. Since an oxide layer that is formed using a low-temperature process is applied to a semiconductor device, the manufacturing process of the semiconductor device is simplified and manufacturing costs may be reduced. | 10-20-2011 |
| 20110305062 | MEMORY CELL AND MEMORY DEVICE USING THE SAME - Provided are a memory cell and a memory device using the same, particularly, a nonvolatile non-destructive readable random access memory cell including a ferroelectric transistor as a storage unit and a memory device using the same. The memory cell includes a ferroelectric transistor having a drain to which a reference voltage is applied, a first switch configured to allow a source of the ferroelectric transistor to be connected to a first line in response to a scan signal, and a second switch configured to allow a gate of the ferroelectric transistor to be connected to a second line in response to the scan signal. The memory device enables random access and performs non-destructive read-out (NDRO) operations. | 12-15-2011 |
| 20120007158 | NON-VOLATILE MEMORY TRANSISTOR HAVING DOUBLE GATE STRUCTURE - Provided is a non-volatile memory transistor having a double gate structure, including a first gate electrode formed on a substrate and to which an operating voltage is applied, a first gate insulating layer formed on the first gate electrode, source and drain electrodes formed on the first gate insulating layer at predetermined intervals, a channel layer formed on the first gate insulating layer between the source and drain electrodes, a second gate insulating layer formed on the channel layer, and a second gate electrode formed on the second gate insulating layer and connected to the first gate electrode such that the operating voltage is applied thereto. Accordingly, a turn-on voltage of the memory transistor can be easily controlled. | 01-12-2012 |
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| 20080301891 | Robot mechanism for cleaning and inspection of live-line insulators - A robot mechanism adopts a dry cleaning method to clean the surface of live-line insulators without: using water and can perform cleaning and inspection of the surface of the live-line insulators while automatically moving along an insulator string. The robot mechanism includes a main unit having upper and lower wing frames connected with each other by a connecting bracket to surround the insulator string, a cleaning unit disposed between the upper and lower wing frames and including a base frame to perform dry cleaning with a rotational brush and a CM guide, a lift unit including a clamp and a ball-bearing screw to move the main unit up or down, and an inspection unit to electrically inspect the insulators; and a coupling unit to couple a pair of the main units to allow the pair of main units to move along a tension insulator string or a suspension insulator string. | 12-11-2008 |
| 20090052605 | HANDLING SYSTEM FOR IN-CORE DETECTOR THIMBLE TUBE OF REACTOR - A handling system for an in-core detector thimble tube of a reactor is disclosed. The handling system serves to withdraw and retract a thimble tube so as to provide a movement path of a movable detector used to measure a neutron flux within a reactor. For this, the handling system basically includes a thimble tube withdrawing/retracting device, which grips the thimble tube using a plurality of synthetic resin pinch rollers to withdraw and retract the thimble tube without any damage to the thimble tube, a thimble tube tensioning device, which applies a constant tensile force to the thimble tube to prevent the thimble tube from shaking or bending upon withdrawing/retracting operations, and a thimble tube platform, which temporarily keeps the withdrawn thimble tube at a fixed position without a risk of shaking of the thimble tube and provides a movement path of the thimble tube tensioning device. With automatic withdrawal/retraction of the thimble tube without damage provides advantages of an extended thimble tube exchange interval, improved safety of system facilities, reduced labor costs and working time, and reduced worker radiation exposure, shortened precaution/maintenance period, and enhanced reactor use efficiency. | 02-26-2009 |
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| 20100158154 | METHOD AND APPARATUS FOR GENERATING PREDISTORTION SIGNAL - Provided is a digital predistortion linearizer applicable to millimeter-wave band point-to-point communications. The digital predistortion linearizer includes a transmission unit and a reception unit. The reception unit receives a first signal including a transmission signal and a distortion signal through a millimeter-wave propagation environment, detects the distortion signal from the first signal, and transmits information on the detected distortion signal with the first signal to the transmission unit. The transmission unit generates a predistortion signal using the information on the distortion signal and the first signal received from the reception unit, couples the generated predistortion signal with the transmission signal, and outputs the coupled signal. | 06-24-2010 |
| 20110073183 | REFLECT-ARRAY LENS FOR SOLAR CELL AND SOLAR CELL MODULE HAVING REFLECT-ARRAY LENS - Disclosed are a reflect-array lens (or a planar lens) and a solar cell module having the same. The reflect-array lens for a solar cell includes: a planar dielectric substrate having a first permittivity, wherein a plurality of recesses are formed on one surface of the planar dielectric substrate and filled with a dielectric having a second permittivity different from the first permittivity. The reflect-array lens can be easily fabricated and has an excellent concentration degree, and the solar cell module having the reflect-array lens has improved photoelectric conversion efficiency. | 03-31-2011 |
| 20110128096 | SYSTEM AND METHOD FOR MODIFYING HAIRPIN FILTER, AND HAIRPIN FILTER - A system for modifying a hairpin filter is provided which includes a structure transformer to divide a hairpin filter into a plurality of filters and to arrange the plurality of filters in a bilaterally symmetrical pattern, and a coupling generator to generate a plurality of coupling lines, each of the plurality of coupling lines being between each of the filters. | 06-02-2011 |
| 20110150131 | APPARATUS AND METHOD FOR PROCESSING DIGITAL TRANSMISSION/RECEPTION SIGNALS TO CORRECT IN-BAND GAIN FLATNESS - An apparatus for processing a digital transmission signal for a transmitter includes a transmission Finite Impulse Response (FIR) filter to perform shaping on initial setting data to convert the initial setting data into a signal having a predetermined passband, a comparator to compare the signal with data including degradation information provided as feedback by a receiver corresponding to the transmitter, to generate a control signal, and a band flatness correction filter to adjust a coefficient of the band flatness correction filter in response to the control signal, and to correct an in-band flatness. | 06-23-2011 |
| 20110249769 | METHOD AND APPARATUS OF COMPENSATION FOR AMPLITUDE AND PHASE DELAY USING SUB-BAND POLYPHASE FILTER BANK IN BROADBAND WIRELESS COMMUNICATION SYSTEM - Provided is a method and apparatus improving a deterioration of a gain flatness and a phase characteristic that may be incurred while a baseband signal is transformed into a immediate frequency (IF) signal and a radio frequency (RF) signal in a broadband wireless communication system. A sub-band extractor may divide the broadband signal into multiple sub-band signals, may pre-compensate for a gain and a phase delay of each sub-band signals in the baseband, and may combine the pre-compensated sub-band signals into the single broadband signal and thus, the deterioration of the gain flatness and a phase delay flatness that may be incurred while the broadband signal is transformed into the IF signal and the RF to signal, may be improved. | 10-13-2011 |
