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Byoung-Moon
Byoung-Moon Hwang, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20090257646 | APPARATUS AND METHOD FOR DETECTING DEFECTS IN WAFER USING LINE SENSOR CAMERA - An apparatus and method for detecting defects in a wafer are provided. An optical part is disposed under an inspection stage and radiates infrared light onto the wafer disposed on an inspection region formed of a transmissive material on the inspection stage. An image obtaining part detects the infrared light transmitted through the wafer disposed on the inspection stage to output an image signal. A conveying part conveys the image obtaining part or the inspection stage in a short side direction of a photographing region of a line sensor included in the image obtaining part, and outputs a pulse signal having a predetermined period corresponding to a relative straight moving distance between the image obtaining part and the inspection stage. A controller counts the pulse signal and outputs a photographing instruction signal controlling the image obtaining part to photograph the wafer whenever the wafer is conveyed in the short side direction of the photographing region of the line sensor toward the image obtaining part by a distance corresponding to the length of short sides of the photographing region. A defect detection part combines each image signal to generate an inspection image corresponding to the wafer, and detects positions of defects existing in the wafer. Each of the line sensors transmits charges accumulated therein to an adjacent line sensor when a photographing instruction signal is input, and then detects the infrared light transmitted through the wafer, and the line sensor positioned at an end in an opposite direction of the conveyance direction outputs charges accumulated therein as the image signal from a time when the number of input photographing signals exceeds the number of line sensors. | 10-15-2009 |
Byoung-Moon Yoon, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20100178754 | METHOD OF MANUFACTURING CMOS TRANSISTOR - A method of manufacturing a complementary metal-oxide semiconductor (CMOS) transistor includes: forming a semiconductor layer in which an n-MOS transistor region and a p-MOS transistor region are defined; forming an insulation layer on the semiconductor layer; forming a conductive layer on the insulation layer; forming a mask pattern exposing the n-MOS transistor region, on the conductive layer; generating a damage region in an upper portion of the conductive layer by implanting impurities in the conductive layer of the n-MOS transistor region using the mask pattern as a mask; removing the mask pattern; removing the damage region; and patterning the conductive layer to form an n-MOS transistor gate and a p-MOS transistor gate. Accordingly, gate thinning and formation of a step between the n-MOS transistor region gate and the p-MOS transistor region gate can be prevented. | 07-15-2010 |
| 20100210068 | Method of forming phase change memory device - Provided is a method of forming a phase change memory device, the method including washing and rinsing a phase change device structure. A phase change material layer may be formed on a semiconductor substrate. The phase change material layer may be etched so as to form a phase change device structure. The semiconductor substrate on which the phase change device structure is formed may be washed using a washing solution including a reducing agent containing fluorine (F), a pH controller, a dissolution agent and water. In addition, the semiconductor substrate on which the washing is performed may be rinsed. | 08-19-2010 |
| 20110136290 | ETCHING METHODS AND METHODS OF MANUFACTURING A CMOS IMAGE SENSOR USING THE SAME - In an etching method, a thin layer is formed on a first surface of a first substrate doped with first impurities having a first doping concentration. The thin layer is doped with second impurities having a second doping concentration lower than the first doping concentration. A second substrate is formed on the thin layer. A second surface of the first substrate is polished. The polished first substrate is cleaned using a cleaning solution including ammonia and deionized water. The cleaned first substrate is etched to expose the thin layer. | 06-09-2011 |
Byoung-Moon Yoon, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080214006 | METHODS OF USING CORROSION-INHIBITING CLEANING COMPOSITIONS FOR METAL LAYERS AND PATTERNS ON SEMICONDUCTOR SUBSTRATES - Provided herein are methods for using corrosion-inhibiting cleaning compositions for semiconductor wafer processing that include an aqueous admixture of at least water, a surfactant and a corrosion-inhibiting compound selected from a group consisting of amino phosphonates, polyamines and polycarboxylic acids. The quantity of the corrosion-inhibiting compound in the admixture is preferably in a range from about 0.0001 wt % to about 0.1 wt % and the quantity of the surfactant is preferably in a range from about 0.001 wt % to about 1.0 wt %. The aqueous admixture may also include sulfuric acid and a fluoride, which act as oxide etchants, and a peroxide, which acts as a metal etchant. | 09-04-2008 |
| 20090067960 | WAFER GUIDE FOR PREVENTING WAFER BREAKAGE IN SEMICONDUCTOR CLEANING APPARATUS - A wafer guide for preventing a wafer breakage in a semiconductor cleaning apparatus includes a lower supporter, side supporters, fixing units and stoppers. The lower supporter is provided with a plurality of slots formed with the same interval in a length direction to vertically stand a plurality of wafers thereon. The side supporters are structured and arranged in parallel at each side above the lower supporter. The side supporters support side end parts of the wafers. The fixing units are adapted to support both end parts of the lower supporter and the side supporters, and may be fixed to a bath. The stoppers are individually coupled to each of the fixing units. The stoppers are operable to generate an error in a close operation of holder units of the robot chuck when the robot chuck deviates from a normal alignment range, so as not to perform a wafer chucking, thereby preventing a wafer breakage during the wafer chucking. | 03-12-2009 |