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Byoung-Ho
Byoung-Ho Choi, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080273449 | OPTICAL RECORDING MEDIUM - An optical recording medium has a user data area and a lead-out area each having grooves and lands formed thereon. Wobbles are formed on at least one lateral surface of the grooves of the user data area and the lead-out area, and configured such that wobble characteristics are made different between the user data area and the lead-out area. Different types of the wobbles are formed on the grooves of either the user data area or the lead-out area, thereby preventing an optical pickup that performs recording/reproducing, from deviating from the user data area. Also, in a multi-layer optical recording medium, a whole area of a recording layer is configured to have the same condition, thereby preventing deterioration in reproducing and/or recording due to a difference in light power transmittance of another recording layer. | 11-06-2008 |
Byoung-Ho Choi, Uijeongbu-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080299379 | COMPOSITE MATERIAL AND METHOD OF MAKING THE COMPOSITE MATERIAL - An improved energy absorbing member comprising, an thermoplastic cellular polymer in contact with a structural element such as a metal guard rail or automotive door, wherein the cellular polymer has an average cell size of at least about 0.75 mm and at least one of C | 12-04-2008 |
| 20090062410 | METHOD OF FORMING EXTRUDED POLYSTYRENE FOAMS AND THE PRODUCTS MADE THEREFROM - The invention a method of forming complex shape of styrenic polymer foams in which a pressing surface is created, for example, by planing/machining a layer of an as formed extruded styrenic polymer plank, contacting said plank with a contoured die face and pressing the foam to form the complex shape. | 03-05-2009 |
Byoung-Ho Kang, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090051783 | Apparatus and method of capturing images having optimized quality under night scene conditions - An apparatus and method of capturing images having an optimized quality during night time conditions is provided. The apparatus for capturing images includes an image-capturing unit that captures an light from an object and generates a first digital image, a night-scene-sensing unit sensing whether the first digital image is a night-scene image, an exposure-adjustment unit adjusting an optimized exposure time by comparing an edge level of the night-scene image with that of a pre-generated reference image if it is sensed that the input image is the night-scene image, and a controller controlling the image-capturing unit to generate a second digital image based on the adjusted exposure time. | 02-26-2009 |
| 20090074396 | Auto-focus method, medium, and apparatus for image-capturing - An auto-focus method, medium, and apparatus for image-capturing. The auto-focus method includes obtaining a first image by placing a focus lens of a corresponding image-capturing apparatus at a first fixed position, obtaining a second image by placing the focus lens at a second fixed position; calculating blur levels of the first and second images, and determining a position of the focus lens by substituting the blur levels of the first and second images into each of a plurality of blur level relational expressions, which are derived from a plurality of pairs of images of respective corresponding objects at different distances from an image sensor module, each of the pairs of images being obtained by placing the focus lens at the first and second fixed positions, respectively. | 03-19-2009 |
Byoung-Ho Kim, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090121691 | Voltage supply device and nonvolatile memory device having the same - A voltage supply device comprises: a charge pump configured to boost a power voltage and to supply the boosted power voltage to a output line; and a voltage control circuit configured to maintain a voltage level of the output line at a target voltage level; wherein the voltage control circuit comprises a reach-through element including a first region and a second region provided in a well, the reach-through element configured to control the voltage level of the output line, using a reach-through function between the first region and the second region. | 05-14-2009 |
| 20090127612 | SEMICONDUCTOR DEVICE HAVING A GATE STRUCTURE - A gate structure in a semiconductor device includes a dielectric layer pattern on a substrate, a floating gate on the dielectric layer pattern, a gate mask on the floating gate, a tunnel insulation layer on the substrate, and a word line on the tunnel insulation layer. The dielectric layer pattern includes a first portion and a second portion having a thickness different from a thickness of the first portion. The floating gate includes a step and tips. The tunnel insulation layer makes contact with a sidewall of the floating gate. The word line extends on a portion of the gate mask. | 05-21-2009 |
Byoung-Ho Kwon, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080206985 | Method of fabricating a semiconductor device - Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region. | 08-28-2008 |
| 20090159952 | METHOD OF FABRICATING NON-VOLATILE MEMORY INTEGRATED CIRCUIT DEVICE AND NON-VOLATILE MEMORY INTEGRATED CIRCUIT DEVICE FABRICATED USING THE SAME - A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures. A damascene metal layer pattern is formed in each of spaces of the first and second pre-stacked gate structures from which the first sacrificial layer pattern is removed, thus completing first and second stacked gate structures. The second sacrificial layer pattern is removed. A stop layer is formed on top surfaces of the first stacked gate structures, top surfaces and side walls of the second stacked gate structures, and a top surface of the substrate. | 06-25-2009 |
Byoung-Ho Lee, Gyeongsangbuk-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20120111081 | METHOD OF MANUFACTURING MAGNESIUM ALLOY PROCESSING MATERIALS WITH LOW CYCLE FATIGUE LIFE IMPROVED BY PRE-STRAINING - The present invention relates to a method of manufacturing magnesium alloy processing materials capable of improving low cycle fatigue life. The manufacturing method for magnesium alloy processing materials with improved low cycle fatigue life comprises pre-straining a magnesium alloy processing material which is processed. | 05-10-2012 |
Byoung-Ho Lee, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080309669 | METHOD AND APPARATUS FOR GENERATING ELEMENTAL IMAGE IN INTEGRAL IMAGING - A method and apparatus for generating an elemental image by an integral image technique are provided. The method includes normalizing coordinates of dots in a frustum formed in perspective projection by mapping the dots in the frustum into a cube; reversing a grade of depth of the cube viewed from a particular viewpoint; and generating a two-dimensional (2D) elemental image necessary for three-dimensional (3D) display from dots in the cube whose grade of depth is reversed. | 12-18-2008 |
| 20100170649 | PROCESS FOR MANUFACTURING POLY(LACTIC ACID) BIO-COMPOSITES.... - Disclosed is a method for manufacturing bio-composites, in which biodegradable poly(lactic acid) (PLA) fibers are mixed, optionally along with general-purpose polypropylene fibers, using a carding process, and compression molded into bio-composites which overcome the problems of the PLA bio-composites manufactured by injection molding, and the PLA bio-composites manufactured thereby. | 07-08-2010 |
Byoung-Ho Lim, Gumsi-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090290083 | Liquid crystal display device and fabrication method thereof - Disclosed is a method of fabricating a liquid crystal display (LCD) device in which a photosensitive film is selectively patterned using a half-tone mask, and then a portion of a passivation layer at a pixel area is selectively removed to secure an penetration path of a stripper. Additionally, a crack is generated on a conductive film formed on a photosensitive film pattern through a predetermined heat treatment to facilitate a lift-off process. Thus, the number of masks can be reduced to simplify the fabrication process of the LCD device and reduce fabrication costs. | 11-26-2009 |
Byoung-Ho Lim, Gyeongbuk KR
| Patent application number | Description | Published |
|---|---|---|
| 20090278129 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A liquid crystal display device includes a gate line and a data line crossing each other to define a pixel region on a substrate, a gate electrode connected to the gate line, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer, source and drain electrodes on the active layer, spaced apart from each other and each having inner sides that face each other, wherein the source electrode is connected to the data line, ohmic contact layers between the active layer and each of the source and drain electrodes, a shielding pattern over the active layer and having outer sides, wherein at least one of the outer sides faces at least one of the inner sides of the source and drain electrodes, and a pixel electrode in the pixel region and connected to the drain electrode. | 11-12-2009 |
Byoung-Ho Park, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100099218 | Method of fabricating a resistance based memory device and the memory device - Example embodiments relate to a method of fabricating a memory device and a memory device. The method of fabricating a memory device comprises forming a lower electrode and an oxide layer on a lower structure and radiating an energy beam on a region of the oxide layer. The memory device comprises a lower structure and an oxide layer and a lower structure formed on the lower structure, the oxide layer including an electron beam radiation region that received radiation from an electron beam source creating an artificially formed current path through the oxide layer to the lower electrode. A reset current of the memory device may be decreased and stabilized. | 04-22-2010 |