Patent application number | Description | Published |
20090089506 | STRUCTURE FOR CACHE FUNCTION OVERLOADING - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a system that includes a cache that stores information in a cache line for processing, wherein the cache line includes at least a first field configured to store an instruction or data and at least a second field configured to store parity information, a parity register that include a parameter indicative a whether parity generation and checking is disabled for the information in the cache line, and a processor that sets the second field in the cache line to include a value, which indicates a corresponding action to be performed, when the parameter in the parity register indicates that parity generation and checking is disabled for the cache line. | 04-02-2009 |
20090089553 | MULTI-THREADED PROCESSING - A system includes a multi-threaded processor that executes an instruction of a process of an executing program. The multi-threaded processor includes at least a first and a second thread. First and second sets of source registers are respectively allocated to the first and second threads, and first and second sets of destination registers are respectively allocated to the first and second threads. A resource prefix configuration register includes mappings between each of the source and destination registers and the threads. The multi-threaded processor, during execution of the instruction by one of the first or the second threads of execution, accesses the source and destination registers based on the mapping, wherein at least one of the accessed registers is allocated to the other of the first or the second thread of execution. | 04-02-2009 |
20090089650 | CACHE FUNCTION OVERLOADING - A method includes checking a first parameter that indicates whether parity generation and checking for a at least a sub-portion of a cache line is disabled, setting at least one parity bit, corresponding to the sub-portion, in the cache line with a second parameter that indicates an action to perform when the first parameter indicates that parity generation and checking is disabled, passing the at least one set parity bit with the sub-portion to a processor for processing, and performing the action when the sub-portion is processed by the processor, wherein the processor performs the action. | 04-02-2009 |
20090089817 | DESIGN STRUCTURE FOR MULTI-THREADED PROCESSING - A design structure embodied in a machine readable storage medium designing, manufacturing, and/or testing a design that includes a multi-threaded processor that executes an instruction of a process of an executing program is provided. The multi-threaded processor includes at least a first and a second thread. First and second sets of source registers are respectively allocated to the first and second threads, and first and second sets of destination registers are respectively allocated to the first and second threads. A resource prefix configuration register includes mappings between each of the source and destination registers and the threads. The multi-threaded processor, during execution of the instruction by one of the first or the second threads of execution, accesses the source and destination registers based on the mapping, wherein at least one of the accessed registers is allocated to the other of the first or the second thread of execution. | 04-02-2009 |
20100250905 | System and Method of Routing Instructions - Disclosed are a method and system for reducing complexity of routing of instructions from an instruction issue queue to appropriate execution pipelines in a superscalar processor. In one or more embodiments, an instruction steering unit of the superscalar processor receives ordered instructions. The steering unit determines that a first instruction and a subsequent second instruction of the ordered instructions are non-branching instructions, and the steering unit stores the first and second instructions in two non-branching instruction issue queue entries of a shadow queue. The steering unit determines whether or not a third instruction the ordered instructions is a branch instruction, where the third instruction is subsequent to the second instruction. If the third instruction is a branch instruction, the steering unit stores the third instruction in a branch entry of the shadow queue; otherwise, the steering unit stores a no operation instruction in the branch entry of the shadow queue. | 09-30-2010 |
20110035643 | System and Apparatus for Error-Correcting Register Files - A method, system and computer program product for enabling a register file to recover from detection of a parity error. A first register file and a second register file are associated with a parallel file structure. When the parity error is detected, the system determines whether the first register file or second register file is associated with the parity error. The register file determined to have the parity error is associated with an offending register and a non-offending register is associated with the “good” register file. Subsequent to the detection of the parity error, the system executes a repair sequence, whereby the register file associated with the offending register receives data from the register file associated with the non-offending register. The offending register file recovers from the parity error with or without the use of a parity interrupt. | 02-10-2011 |
Patent application number | Description | Published |
20120144165 | SIDEBAND PAYLOADS IN PSEUDO NO-OPERATION INSTRUCTIONS - A pseudo no-op instruction in an instruction stream is detected, and the pseudo no-op instruction is decoded as being an opcode, wherein a parameter of the pseudo no-op instruction uniquely identifies the opcode. The method makes use of a pseudo no-op instruction and provides the pseudo no-op instruction with additional semantics outside of the instruction stream execution. New or enhanced functionality can be implemented in application software in a fashion that fully preserves backward compatibility to software and processors that do not support the new or enhanced functionality. If these functionalities are not supported, then the legacy software or processor will merely see and execute the pseudo no-op instruction, which will effectively do nothing at all. | 06-07-2012 |
20120151185 | FINE-GRAINED PRIVILEGE ESCALATION - A processor and a method for privilege escalation in a processor are provided. The method may comprise fetching an instruction from a fetch address, where the instruction requires the processor to be in supervisor mode for execution, and determining whether the fetch address is within a predetermined address range. The instruction is filtered through an instruction mask and then it is determined whether the instruction, after being filtered through the mask, equals the value in an instruction value compare register. The processor privilege is raised to supervisor mode for execution of the instruction in response to the fetch address being within the predetermined address range and the filtered instruction equaling the value in the instruction value compare register, wherein the processor privilege is raised to supervisor mode without use of an interrupt. The processor privilege returns to its previous level after execution of the instruction. | 06-14-2012 |
20130262815 | HYBRID ADDRESS TRANSLATION - Embodiments of the invention relate to hybrid address translation. An aspect of the invention includes receiving a first address, the first address referencing a location in a first address space. The computer searches a segment lookaside buffer (SLB) for a SLB entry corresponding to the first address; the SLB entry comprising a type field and an address field and determines whether a value of the type field in the SLB entry indicates a hashed page table (HPT) search or a radix tree search. Based on determining that the value of the type field indicates the HPT search, a HPT is searched to determine a second address, the second address comprising a translation of the first address into a second address space; and based on determining that the value of the type field indicates the radix tree search, a radix tree is searched to determine the second address. | 10-03-2013 |
20130262817 | HYBRID ADDRESS TRANSLATION - Embodiments of the invention relate to hybrid address translation. An aspect of the invention includes receiving a first address, the first address referencing a location in a first address space. The computer searches a segment lookaside buffer (SLB) for a SLB entry corresponding to the first address; the SLB entry comprising a type field and an address field and determines whether a value of the type field in the SLB entry indicates a hashed page table (HPT) search or a radix tree search. Based on determining that the value of the type field indicates the HPT search, a HPT is searched to determine a second address, the second address comprising a translation of the first address into a second address space; and based on determining that the value of the type field indicates the radix tree search, a radix tree is searched to determine the second address. | 10-03-2013 |
20130339651 | MANAGING PAGE TABLE ENTRIES - Embodiments relate to managing page table entries in a processing system. A first page table entry (PTE) of a page table for translating virtual addresses to main storage addresses is identified. The page table includes a second page table entry contiguous with the second page table entry. It is determined whether the first PTE may be joined with the second PTE, based on the respective pages of main storage being contiguous. A marker is set in the page table for indicating that the main storage pages identified by the first PTE and second PTEs are contiguous. | 12-19-2013 |
20130339652 | Radix Table Translation of Memory - Embodiments relate to managing memory page tables in a processing system. A request to access a desired block of memory is received. The request includes an effective address that includes an effective segment identifier (ESID) and a linear address, the linear address including a most significant portion and a byte index. An entry in a buffer that includes the ESID of the effective address is located. Based on the entry including a radix page table pointer (RPTP), performing: using the RPTP to locate a translation table of a hierarchy of translation tables, using the located translation table to translate the most significant portion of the linear address to obtain an address of a block of memory, and based on the obtained address, performing the requested access to the desired block of memory. | 12-19-2013 |
20130339653 | Managing Accessing Page Table Entries - A system for accessing memory locations includes translating, by a processor, a virtual address to locate a first page table entry (PTE) in a page table. The first PTE includes a marker and an address of a page of main storage. It is determined whether a marker is set in the first PTE. The system identifies a large page size of a large page associated with the first PTE based on determining that the marker is set in the first PTE. The large page consists of contiguous pages of main storage. An origin address of the large page is determined based on determining that the marker is set in the first PTE. The virtual address is used to index into the large page at the origin address to access main storage. | 12-19-2013 |
20130339654 | Radix Table Translation of Memory - A method includes receiving a request to access a desired block of memory. The request includes an effective address that includes an effective segment identifier (ESID) and a linear address, the linear address comprising a most significant portion and a byte index. Locating an entry, in a buffer, the entry including the ESID of the effective address. Based on the entry including a radix page table pointer (RPTP), performing, using the RPTP to locate a translation table of a hierarchy of translation tables, using the located translation table to translate the most significant portion of the linear address to obtain an address of a block of memory, and based on the obtained address, performing the requested access to the desired block of memory. | 12-19-2013 |
20130339658 | MANAGING PAGE TABLE ENTRIES - A method includes identifying, by a processor, a first page table entry (PTE) of a page table for translating virtual addresses to main storage addresses, the page table comprising a second page table entry contiguous with the second page table entry, determining with the processor whether the first PTE may be joined with the second PTE, the determining based on the respective pages of main storage being contiguous, and setting a marker in the page table for indicating that the main storage pages of identified by the first PTE and second PTEs are contiguous. | 12-19-2013 |
20130339659 | MANAGING ACCESSING PAGE TABLE ENTRIES - A method for accessing memory locations includes translating, by a processor, a virtual address to locate a first page table entry (PTE) in a page table. The first PTE includes a marker and an address of a page of main storage. It is determined, by the processor, whether a marker is set in the first PTE. A large page size of a large page associated with the first PTE is identified based on determining that the marker is set in the first PTE. The large page is made up of contiguous pages of main storage. An origin address of the large page is determined based on determining that the marker is set in the first PTE. The virtual address is used to index into the large page at the origin address to access main storage. | 12-19-2013 |
20140006903 | Utilizing Error Correcting Code Data Associated With A Region of Memory | 01-02-2014 |
Patent application number | Description | Published |
20140101359 | ASYMMETRIC CO-EXISTENT ADDRESS TRANSLATION STRUCTURE FORMATS - An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated. | 04-10-2014 |
20140101404 | SELECTABLE ADDRESS TRANSLATION MECHANISMS - An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration, and the use of a particular translation structure format in translating an address is selectable. | 04-10-2014 |
20140101407 | SELECTABLE ADDRESS TRANSLATION MECHANISMS - An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration, and the use of a particular translation structure format in translating an address is selectable. | 04-10-2014 |
20140101408 | ASYMMETRIC CO-EXISTENT ADDRESS TRANSLATION STRUCTURE FORMATS - An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated. | 04-10-2014 |
20140281209 | HARDWARE-BASED PRE-PAGE WALK VIRTUAL ADDRESS TRANSFORMATION - An indication of a virtual address is received. A current page size of a plurality of available page sizes is read from a register. A shift amount is determined based, at least in part, on the current page size. A bit shift of the virtual address is performed in which the virtual address is bit shifted by, at least, the determined shift amount. | 09-18-2014 |
20140281353 | HARDWARE-BASED PRE-PAGE WALK VIRTUAL ADDRESS TRANSFORMATION - An apparatus includes a processor and a virtual address transformation unit coupled with the processor. The virtual address transformation unit includes a register. The virtual address transformation unit is configured to receive an indication of a virtual address and read, from the register, a current page size of a plurality of available page sizes. The virtual address transformation unit is also configured to determine a shift amount based, at least in part, on the current page size and perform a bit shift of the virtual address, wherein the virtual address is bit shifted by, at least, the determined shift amount. | 09-18-2014 |
Patent application number | Description | Published |
20090106009 | RECONSTRUCTION OF DATA FROM SIMULATION MODELS - Systems and media for reconstructing data from simulation models are disclosed. Embodiments may include a media containing instructions for accessing an alias from an alias file. The media may include instructions for searching for a net name and, if the net name is not found, searching an alias index file for an alias index entry associated with the net name, the alias index entry having a net name and an associated position. The instructions may also include, if the net name entry is found, instructions for accessing from an alias file an alias associated with the net name. A further embodiment may include instructions for receiving a net name and a position of an alias in the alias file, creating an alias index entry for the alias having a net name and the position of the alias, and storing the created alias index entry in the alias index file. | 04-23-2009 |
20090112556 | RECONSTRUCTION OF DATA FROM SIMULATION MODELS - Systems, method, and media for reconstructing data from simulation models are disclosed. Embodiments may include a method for accessing an alias from an alias file. The method may generally include searching for a net name and, if the net name is not found, searching an alias index file for an alias index entry associated with the net name, the alias index entry having a net name and an associated position. The method may also generally include, if the net name entry is found, accessing from an alias file an alias associated with the net name. A further embodiment may generally include receiving a net name and a position of an alias in the alias file, creating an alias index entry for the alias having a net name and the position of the alias, and storing the created alias index entry in the alias index file. | 04-30-2009 |