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Burkart, TX

Scott Burkart, Royse City, TX US

Patent application numberDescriptionPublished
20100279745MOBILE COMMUNICATION DEVICE AND COMMUNICATION METHOD - A mobile communication device includes a processor; a data acquisition device for acquiring data and providing it to the processor; a transceiver for transmitting at least some of the acquired data to an external device; and a low-power clock. The low-power clock counts down a random delay time period and temporarily shifts the processor and the transceiver from low-power sleep modes to active wake modes so that the processor and transceiver can transmit at least some of the acquired data to the external device while in their active wake modes.11-04-2010

Scott M. Burkart, Royse City, TX US

Patent application numberDescriptionPublished
20100157854SYSTEMS AND METHODS FOR SENDING DATA PACKETS BETWEEN MULTIPLE FPGA DEVICES - Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Dynamically-sized data packets, sized in accordance with the amount of data ready to be sent, are transferred between the devices and/or interfaces on the card.06-24-2010
20100169403SYSTEM FOR MATRIX PARTITIONING IN LARGE-SCALE SPARSE MATRIX LINEAR SOLVERS - A system for solving large-scale matrix equations comprises a plurality of field programmable gate arrays (FPGAs), a plurality of memory elements, a plurality of memory element controllers, and a plurality of processing elements. The FPGAs may include a plurality of configurable logic elements and a plurality of configurable storage elements. The memory elements may be accessible by the FPGAs and may store a matrix and a first vector. The memory element controllers may be formed from configurable logic elements and configurable storage elements and may supply at least a portion of a row of the matrix and at least a portion of the first vector. Each processing element may receive at least the row of the matrix and the first vector and solve an iteration for one element of the first vector.07-01-2010
20100277280Systems and methods for relaying information with RFID tags - Data from one or more sensors may be collected using a first band of a multi-band RFID tag device and then passed on to a remote receiver from the RFID tag device using a second RF band. This capability may be employed to allow a first band-equipped RFID tag to collect data from local sensors, and then to report that data over a second band link, allowing the RFID tag device to function as an intermediary bridge device or relay between the sensor/s and a remote receiver and/or tag interface device. Such a remote receiver may further be in communication with a remote network so that the RFID tag device acts to bridge local sensor data to a remote network, where it may be further processed aid/or accessed by one or more users. The RFID tag device may also be interactive in nature, meaning that the tag data storage and/or the tag's operation is reprogrammable in the operational environment.11-04-2010
20100277283Systems and methods for RFID tag operation - A RFID tag system may be configured as a tag having a first band (e.g., multiple channel-based NBFM frequency band) transceiver to allow field programmability of tag behavior and onboard tag data. The RFID tag system may be configured to collect data from one or more local sensors through the first band link and store data points of interest in tag onboard storage. The RFID tag system may be configured to work in conjunction with a remote interrogating unit, and a handheld device or other local interrogating unit may be additionally or alternatively provided to communicate with such aRFID tag. Data that is stored on the RFID tag may be retrieved or changed, and/or the operation of the tag may be modified.11-04-2010
20100277284Data separation in high density environments - Systems and methods for data separation, which may be employed to receive and process RFID tag data in RF signal environments where multiple RFID tags are tracked, localized and/or employed to transmit information. The disclosed systems and methods may be implemented for data separation in a high density aRFID environment using RFID tags in combination with spatial and/or frequency separation.11-04-2010
20100277285Systems and methods for communication with RFID tags - Communication between a multi-band RFID tag device that communicates on first and second bands with other devices may be enabled, using a bidirectional communication bridging device that converts first band signals of the RFID tag device to third band signals of another device, and vice-versa. Examples of third band-capable devices that may be bridged for communication with the first band of a RFID tag device include WiFi devices such as smart phone, notebook computer, WLAN router or any other type of WiFi enabled device. In one example, a tag interface control device may be provided in the form of a WiFi-enabled handheld unit that communicates with a multi-band RFID tag through a bridging device using NBFM radio frequency (RF) communications to retrieve or change stored data and/or change the tag operation. Such a WiFi-enabled handheld unit may be configured to be relatively small, portable, and/or battery or wireless-powered.11-04-2010
20100277286Synchronization of devices in a RFID communications environment - An adaptive wakeup methodology may be implemented to allow an radio frequency identification (RFID) tag to stay synchronized with periodic radio frequency (RF) interrogator polling signal while at the same time optimizing power consumption. A receiver (or transceiver) component of a RFID tag may only be operated when an interrogator polling signal is expected, and in a manner that reduces the amount of time between when the receiver or transceiver is turned on and when the interrogator polling signal is received (i.e., the receive buffer time). At other times, the RFID tag may be placed in a low power consumption sleep state. The amount of time that the RFID tag spends in such a low power sleep state before waking and receiving the following interrogator polling signal may also be optionally adjusted, e.g., to fit characteristics of a given situation and/or to re-synchronize a given aRFID tag with first band transmissions from an aRFIDI.11-04-2010

Scott Michael Burkart, Royse City, TX US

Patent application numberDescriptionPublished
20090172052TILED ARCHITECTURE FOR STATIONARY-METHOD ITERATIVE LINEAR SOLVERS - A system for solving linear equations comprises a first circuit including a first multiplication module for multiplying a first row of a matrix by a first instance of a vector variable to generate a first product, and a first linear solver module for calculating an updated first element of the vector variable using the first product. A second circuit includes a second multiplication module for multiplying a second row of the matrix by a second instance of the vector variable to generate a second product, and a second linear solver module for calculating an updated second element of the vector variable using the second product. An interface module updates the second instance of the vector variable with the first updated element, and updates the first instance of the vector variable with the second updated element.07-02-2009
20090282207SYSTEM & METHOD FOR STORING A SPARSE MATRIX - A system and method for storing and retrieving a sparse matrix from memory of a computing device while minimizing the amount of data stored and costly jumps in memory. The computing device may be an FPGA having memory and processing elements. The method comprises storing non-zero data elements of the matrix in a data array and storing their corresponding column address values in a column index array. To read this stored data from memory, each preceding value of the column index array may be compared with each current value of the column index array to determine if the data array value corresponding with the current column index array value belongs on the next row of the matrix. The method may include pre-ordering the matrix with zero-pad placeholders or creating a row increment pointer array which typically stores fewer values than the number of rows in the matrix.11-12-2009