Patent application number | Description | Published |
20080198944 | POWER TRANSMISSION APPARATUS IN WIRELESS COMMUNICATION SYSTEMS - An envelope elimination and restoration power transmission apparatus in a wireless communication system is provided. The apparatus comprises a signal processor for dividing a transmission signal into a size component and a phase component and for generating a control signal for controlling a current of a bias modulator according to the size component, the bias modulator for amplifying the size component according to the control signal supplied from the signal processor, for lowering an impedance characteristic of the amplified size component and for outputting the amplified size component, a frequency modulator for modulating the phase component into a radio frequency (RF) signal, and a power amplifier for amplifying the RF signal by using an output signal of the bias modulator as a bias voltage. As provided, the transmission apparatus reduces a memory effect due to an impedance difference in a modulation frequency band. | 08-21-2008 |
20090212861 | LOW NOISE AMPLIFIER - A low noise amplifier is provided. The low noise amplifier includes: a low noise amplifying unit amplifying an input signal; a harmonic and noise generating unit disposed in an input terminal of the low noise amplifying unit, for generating a compensating signal for compensating for an intermodulation distortion signal and a thermal noise signal of the input signal to the low noise amplifying unit; and a load unit outputting the amplified input signal generated by the low noise amplifying unit. | 08-27-2009 |
20090215413 | APPARATUS AND METHOD FOR POWER TRANSMITTER IN WIRELESS COMMUNICATION SYSTEM - An apparatus and a method for an Envelope Elimination and Restoration (EER) power transmitter are provided. The apparatus includes a signal separator for splitting a transmit signal to an amplitude component and a phase component, an orthogonal modulator for modulating the phase component into a Radio Frequency (RF) signal, a bias modulator for linearly amplifying the amplitude component, for determining a bias voltage according to a magnitude of the amplitude component, and for providing a current generated using the determined bias voltage to a high-efficiency power amplifier and the high-efficiency power amplifier for amplifying the RF signal using the linearly amplified amplitude component as a drain bias voltage and using the generated current as a drain bias current. | 08-27-2009 |
20090215421 | RF RECEIVER AND METHOD OF RECEIVING RF SIGNAL - A radio frequency (RF) receiver and a method of receiving an RF signal are provided. The RF receiver includes a low-noise amplifying unit which amplifies a received signal while restricting out-of-band interferer of the received signal, a sampling unit which performs sampling to convert the amplified signal to a discrete time domain signal, a frequency translation unit which down-converts the sampled signal into a frequency band that enables the sampled signal to be converted into a digital signal and restricts interferer from a frequency within an aliasing band according to a sampling frequency, an anti-aliasing filtering unit which prevents aliasing from the down-converted signal, a clock unit which provides the sampling unit, the frequency translation unit, and the anti-aliasing filtering unit with sampling frequencies, and an analog-digital-converter which converts the converted signal into the digital signal. | 08-27-2009 |
20090327793 | FINITE IMPULSE RESPONSE (FIR) FILTER WITHOUT DECIMATION - Provided is a discrete signal finite impulse response (FIR) filter and a filter set in which a plurality of FIR filter units are connected in a cascade structure to remove down-sampling by decimation, in order to improve the attenuation characteristics of a FIR filter, such as, for example, a switched capacitor filter. The FIR filter includes a clock generator generating a plurality of clock signals that are different from each other; and N+2 sub blocks each including N sample storage units, each sample storage unit storing a received sample. Each sub block being in a state among a number of possible states including N charging states for storing the received sample, a transfer state for outputting the stored sample and a reset state for operation initialization. The N charging states, the transfer state and the reset state are changed sequentially in response to the clock signals. | 12-31-2009 |
20100188153 | High-efficiency power amplification apparatus using saturated operation and method for controlling the same - A saturated power amplification apparatus and a method for controlling the same are provided, in which a power device is provided, and an output matcher matches a load impedance of the power device. The load impedance is a complex impedance exceeding an impedance generated during power matching in the saturated power amplification apparatus. | 07-29-2010 |
20110204974 | APPARATUS FOR IMPROVING PERFORMANCE AT LOW POWER REGION IN A DOHERTY AMPLIFIER - A method and apparatus improve the performance of a carrier amplifier in a Doherty amplifier. The Doherty amplifier includes a power divider, a carrier amplifier, at least one peaking amplifier, offset lines, and a Doherty circuit. The power divider provides a power signal to each of the carrier amplifier and the at least one peaking amplifier. The carrier amplifier amplifies power of a signal inputted from the power divider. The at least one peaking amplifier amplifies power of a signal inputted from the power divider. The offset lines control a load impedance when the at least one peaking amplifier does not operate. When the at least one peaking amplifier does not operate, the Doherty circuit generates the load impedance of the carrier amplifier that is larger than twice a load impedance at the maximum output power of the carrier amplifier. | 08-25-2011 |
20120086507 | POWER AMPLIFIER LINEARIZATION METHOD AND APPARATUS - Disclosed is a method and apparatus for linearizing a power amplifier using a digital signal process (DSP), and particularly, is a method and apparatus for effectively linearizing an amplifier which has a plurality of distortion generating sources. To this end, there is a plurality of compensation methods and compensation units which can generate inverse distortion signals corresponding to the distortion components outputted by the plurality of distortion generating sources, thereby making it possible to provide superior linearity. | 04-12-2012 |
20120126891 | POWER AMPLIFICATION APPARATUS - A power amplification apparatus includes a first amplifier turned on at a preset low input power; and a second amplifier connected in parallel with the first amplifier and turned off at a low input power due to a relatively low bias current. Output capacitors of the first amplifier and the second amplifier are compensated for by inductors or microstrip lines of dc power supply paths. An output matching circuit of the first amplifier includes a λ/4 transformer. An output matching circuit of the second amplifier has the phase of 0°. Input matching circuits of the first amplifier and the second amplifier include delay compensation circuits. The output matching circuit of the first amplifier, the output matching circuit of the second amplifier, and a final output matching circuit have the same impedance transformation rates. | 05-24-2012 |
20120326787 | VARIABLE-GAIN AMPLIFIER CIRCCUIT AND RECEIVER INCLUDING THE SAME - A variable-gain amplifier (VGA) circuit comprises a plurality of cascaded VGAs each having a gain that varies linearly according to a gain control voltage. The VGA circuit has an overall gain that varies exponentially according to the gain control voltage without the use of an exponential function generator circuit. | 12-27-2012 |
20130193948 | LOW POWER CIRCUIT FOR REDUCING LEAKAGE POWER USING NEGATIVE VOLTAGE - A power circuit for reducing a leakage power using a negative voltage is provided. The power circuit includes a current source including a transistor including a gate. The power circuit further includes a current source control circuit connected to the gate of the transistor, and configured to apply a positive voltage to the gate of the transistor if the current source is to operate in an active mode, and apply the negative voltage to the gate of the transistor if the current source is to operate in an inactive mode. | 08-01-2013 |
20130241657 | MULTI-MODE DOHERTY POWER AMPLIFIER - The present invention relates to a Doherty power amplifier in which a new operation mode for accomplishing high efficiency at a lower output power level is added to operation of a conventional Doherty power amplifier, thereby achieving high efficiency at various output power levels of the power amplifier. The multi-mode Doherty power amplifier to which a second power mode is added may be reduced in size so as to be integrated into a chip. | 09-19-2013 |
20140335804 | TRANSMITTER FOR SUPPORTING MULTIMODE AND MULTIBAND USING MULTIPLE RADIO FREQUENCY (RF) DIGITAL-TO-ANALOG CONVERTERS (DAC) AND CONTROL METHOD OF THE TRANSMITTER - A transmitter configured to support a multimode and a multiband, using radio frequency (RF) digital-to-analog converters (DACs), includes a first RF DAC configured to transmit a first signal in a first frequency band, and a second RF DAC configured to transmit a second signal in a second frequency band different from the first frequency band. The transmitter further includes an impedance controller configured to adjust impedance of one of the first RF DAC and the second RF DAC operating in an impedance matching mode to adjust a frequency range of another one of the first RF DAC and the second RF DAC operating in a data transmission mode. | 11-13-2014 |