Bulusu
Atchyuta Rama Chandra Murty Bulusu, Perchtoldsdorf AT
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20100035987 | PLEUROMUTILIN DERIVATIVES FOR THE TREATMENT OF DISEASES MEDIATED BY MICROBES - A pleuromutilin derivative compound of general formula (I) | 02-11-2010 |
20120029072 | PLEUROMUTILIN DERIVATIVES FOR THE TREATMENT OF DISEASES MEDIATED BY MICROBES - Disclosed are pleuromutilin derivatives of formula (I) | 02-02-2012 |
20120232047 | SUBSTITUTED CLAVULANIC ACID - The present invention relates to compounds of formula I | 09-13-2012 |
20130040954 | PLEUROMUTILIN DERIVATIVES FOR THE TREATMENT OF DISEASES MEDIATED BY MICROBES - Pleuromutilin derivative compounds of the following formula, and uses thereof for the treatment of diseases mediated by microbes, are disclosed: | 02-14-2013 |
20140256731 | PLEUROMUTILIN DERIVATIVES FOR THE TREATMENT OF DISEASES MEDIATED BY MICROBES - Pleuromutilin derivative compounds of the following formula, and uses thereof for the treatment of diseases mediated by microbes, are disclosed: | 09-11-2014 |
Bhanu Teja Bulusu, Hyderabad IN
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20080286373 | Ziprasidone formulations - A ziprasidone formulation containing at least (a) one ziprasidone compound and at least an excipient component (b) that includes at least one of | 11-20-2008 |
20080319048 | Solubilized formulation of docetaxel without tween 80 - Lyophilizates containing docetaxel and the use thereof in preparing concentrated liquid formulations, and ready to use formulations for injection, as well as such concentrates and ready to use formulations themselves are disclosed in which Tween surfactants are avoided so that hypersensitivity reactions to Tween surfactants can be avoided and docetaxel can be administered at higher doses and/or for longer periods of time and/or for additional treatment cycles. | 12-25-2008 |
20120264817 | SOLUBILIZED FORMULATION OF DOCETAXEL WITHOUT TWEEN 80 - Lyophilizates containing docetaxel and the use thereof in preparing concentrated liquid formulations, and ready to use formulations for injection, as well as such concentrates and ready to use formulations themselves are disclosed in which Tween surfactants are avoided so that hypersensitivity reactions to Tween surfactants can be avoided and docetaxel can be administered at higher doses and/or for longer periods of time and/or for additional treatment cycles. | 10-18-2012 |
Chandra Sekhar Veera Venkata Naga Bulusu, Hyderabad IN
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20090263475 | DEXLANSOPRAZOLE COMPOSITIONS - Premixes of dexlansoprazole with pharmaceutical excipients, processes for preparing premixes, pharmaceutical formulations containing the premixes, and their use in treatment of erosive esophagitis and heartburn associated with non-erosive gastroesophageal reflux disease. | 10-22-2009 |
20120231073 | DEXLANSOPRAZOLE COMPOSITIONS - Premixes of dexlansoprazole with pharmaceutical excipients, processes for preparing premixes, pharmaceutical formulations containing the premixes, and their use in treatment of erosive esophagitis and heartburn associated with non-erosive gastroesophageal reflux disease. | 09-13-2012 |
Gopi Kumar Bulusu, Tamil Nadu IN
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20090199089 | Converting a Heterogeneous Document - A method for transforming a heterogeneous compound document to a desired format based on a prescribed model is provided. The method comprises the steps of: (i) specifying the components of the heterogeneous compound document as a hierarchical tree structure in multiple formats and specifying the input sources of information for each of the components as part of the model; verifying and composing the heterogeneous compound document using a modeling language parser and a document composer by dynamically obtaining input information from the sources specified in the model and (iii) converting the input compound document to the desired format using the document composer. A system for performing the abovementioned method is also provided. | 08-06-2009 |
Gopi Kumar Bulusu, Vasakhapatnam IN
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20110023008 | METHOD FOR OPTIMIZING AN ARCHITECTURAL MODEL OF A MICROPROCESSOR - A method for optimizing an architectural model of a microprocessor includes representing an instruction set of the microprocessor as a graph by configuring the elements of the instruction set as nodes of the graph. Determination is made whether the nodes with identical bit position and value encoding is present in the graph. If the nodes with the identical bit position and value encoding are present, a path from a source node to a target node is separated into a common node for each node in the graph. The common node is reused to optimize common paths out of the graph and the source node is directly connected to the common node in the graph using a forward edge. A back-edge is added from the common node to the source node through the target node and the above steps are recursively repeated until all the nodes of the graph are processed. | 01-27-2011 |
20130074030 | METHOD, COMPUTER PROGRAM AND COMPUTING SYSTEM FOR OPTIMIZING AN ARCHITECTURAL MODEL OF A MICROPROCESSOR - A computer program for optimizing an architectural model of a microprocessor by configuring elements of the instruction set as nodes of the graph. The architectural model of a microprocessor represents an instruction set of the microprocessor. Determination is made whether nodes with identical bit position and value encoding are in the graph. If nodes with the identical bit position and value encoding are present, a path from a source node to a target node is separated into a common node for each node in the graph. The common node is reused to optimize common paths from the graph and the source node is directly connected to the common node in the graph using a forward edge. A back-edge is added from the common node to the source node through the target node and the above steps are recursively repeated until all nodes of the graph are processed. | 03-21-2013 |
Mallik Bulusu, Bellevue, WA US
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20150067163 | LOCATION AWARE RESOURCE LOCATOR - Systems and methods providing a location-aware resource locator model for facilitating communication with networked electronic devices are generally disclosed herein. One embodiment includes a resource locator using a standard Uniform Resource Locator (URL) format, but enabling identification of one or many devices based on logical location information provided in the resource locator. The resource locator may also enable identification of the one or many devices based on logical proximity information (such as a logical term indicating a location property) relative to a dynamic location. Further disclosed embodiments include uses of a hierarchical structure to define logical terms and classes for use with a resource locator, and various location determination and lookup techniques used in connection with accessing an electronic device. | 03-05-2015 |
Mallik Bulusu, Olumpia, WA US
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20130318577 | TRUSTED APPLICATION MIGRATION ACROSS COMPUTER NODES - An embodiment includes a secure and stable method for sending information across a compute continuum. For example, the method may include executing an application (e.g., video player) on a first node (e.g., tablet) with a desire to perform “context migration” to a second node (e.g., desktop). This may allow a user to watch a movie on the tablet, stop watching the movie, and then resume watching the movie from the desktop. To do so in a secure and stable manner, the first node may request security and performance credentials from the second node. If both credential sets satisfy thresholds, the first node may transfer content (e.g., encrypted copy of a movie) and state information (e.g., placeholder indicating where the movie was when context transfer began). The second node may then allow the user to resume his or her movie watching from the desktop. Other embodiments are described herein. | 11-28-2013 |
Millik Bulusu, Olympia, WA US
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20120079259 | METHOD TO ENSURE PLATFORM SILICON CONFIGURATION INTEGRITY - Some aspects include beginning a power on self test (POST) by a BIOS for a computer system; enumerating the computer system by the BIOS; providing, based on the enumeration of the computer system by the BIOS, at least one configuration setting of the computer system to a management engine (ME) of the computer system; and applying a lock to the at least one configuration setting by the ME to manage a change to the at least one configuration setting, all prior to an ending of the POST. | 03-29-2012 |
Prashant Bulusu, Peoria, IL US
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20140084628 | ROLL-OVER PROTECTION STRUCTURE - A roll-over protective structure for a frame structure of a cab assembly including an outer tube and an inner tube disposed within the outer tube at a pre-determined location to define a composite tube. The composite tube has an upright support with an end portion, and a transverse support connecting the upright support to define a curved corner. Further, the composite tube may have a U-shaped configuration. The composite tube may be further shaped through a hydroforming process to achieve a desired cross-section at the pre-determined location. For example, the curved corner may have a first cross-section, and the end portion may have a second cross-section. | 03-27-2014 |
Ravi Bulusu, San Jose, CA US
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20090259862 | CLOCK-GATED SERIES-COUPLED DATA PROCESSING MODULES - A clock module is coupled in parallel to a number of data processing modules that are coupled in series. The data processing modules can be individually clock-gated. Each of the data processing modules can determine whether or not it can be placed into an idle state. To reduce power consumption, any subset of the data processing modules that are eligible to be placed in an idle state can be clock-gated. The remaining data processing modules can continue to receive clock signals from the clock module and thus can continue to process data. | 10-15-2009 |
Ravi Bulusu, Santa Clara, CA US
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20100104008 | METHOD AND SYSTEM FOR PERFORMING TWO-DIMENSIONAL TRANSFORM ON DATA VALUE ARRAY WITH REDUCED POWER CONSUMPTION - A method and system for performing a 2D transform is disclosed. The 2D transform may include a row transform and/or a column transform. When performing the row or column transform, it may be determined whether each of different subsets of the data values including a partition of a row or column includes at least one zero value, whether each of different subsets of a first subset of the partition includes at least one zero value, and whether each of different subsets of at least one other subset of the partition includes at least one zero value. When performing the row or column transform, at least one transformation operation on at least one zero value may be bypassed or performed in a reduced-power manner, where such transformation operation would otherwise be performed in a manner consuming full power if the zero value were a non-zero value. | 04-29-2010 |
Ravi Bulusu, Hyderabad IN
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20140105272 | LOW POWER CONTEXT ADAPTIVE BINARY ARITHMETIC DECODER ENGINE - A technique for decoding data within a context-based adaptive binary arithmetic coding (CABAC) stream processes one or more bins of compressed data based on video format parameters associated with the stream. A configurable CABAC decoder circuit cascades one or more instances of CABAC bin decoder logic to operate properly within a timing constrain established by a decoder clock frequency. The decoder may advantageously select among different combinations of decoder clock frequency and decoded bins per clock cycle to minimize power consumption associated with decompressing and playing the compressed data. | 04-17-2014 |
Ravi Prasad Bulusu, Hyderabad IN
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20140344827 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR SCHEDULING A TASK TO BE PERFORMED BY AT LEAST ONE PROCESSOR CORE - A system, method, and computer program product are provided for scheduling a task to be performed by at least one processor core. In operation, a task to be performed by at least one of a plurality of processor cores is identified. Additionally, a temperature of each of the plurality of processor cores is determined. Further, a first processor core of the plurality of processor cores is identified based on at least the determined temperature of each of the plurality of processor cores and, in one embodiment, spatial information associated with each of the plurality of processor cores. Still yet, at least a portion of the task is scheduled to be performed by the first processor core. | 11-20-2014 |
Shekher Bulusu, Fremont, CA US
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20110131302 | MINIMUM DISRUPTION MST RECONFIGURATION (MDMR) - In one embodiment, a first multiple spanning tree (MST) region configuration for an MST process may be maintained at a switch in a computer network, where the first configuration has a virtual local area network (VLAN)-to-instance (VI) mapping that maps each of one or more VLANs to one of one or more MST instances in the MST region. The switch may subsequently receive a second MST region configuration that has a different VI mapping than the first configuration, and may determine one or more VLANs of the second configuration that have a different VI mapping from the first configuration (“affected VLANs”). Accordingly, in response to a trigger to apply the second configuration at the switch, the affected VLANs are blocked for a delay, and the second configuration may be applied at the switch without restarting the MST process. | 06-02-2011 |
20110261724 | SHARED VIRTUAL DEVICE PORTS - In one embodiment, a solution is provided wherein multiple virtual devices may be configured on the same physical port of a network device. For example, a first virtual device and a second virtual device may be configured to use the same physical port. A single internal spanning tree instance may be configured for both the first virtual device and the second virtual device. | 10-27-2011 |
20120113871 | SYSTEM AND METHOD FOR PROVIDING A LOOP FREE TOPOLOGY IN A NETWORK ENVIRONMENT - An example method is provided and includes executing an intermediate system to intermediate system (IS-IS) protocol for a first set of network links in a network. The method also includes executing a spanning tree protocol (STP) for a second set of network links, and generating a network topology that includes using a broadcast tree system identifier (ID) as a root bridge ID for the network. The method further includes communicating the root bridge ID to a neighboring network element. In more specific examples, an STP block is communicated to a redundant link, which connects a first switch and a second switch. The first and second switches can converge on the network topology using the broadcast tree system ID. | 05-10-2012 |
20120224510 | SYSTEM AND METHOD FOR MANAGING TOPOLOGY CHANGES IN A NETWORK ENVIRONMENT - A method is provided in one example embodiment and includes receiving a spanning tree protocol topology change notification (STP TCN) in a network; removing topology data for a first plurality of gateways associated with a first network segment ID that is shared by a particular gateway that communicated the STP TCN; and communicating an edge TCN to a second plurality of gateways associated with a second network segment ID and for which topology data has not been removed based on the STP TCN. | 09-06-2012 |
20140112203 | Enhanced Fine-Grained Overlay Transport Virtualization Multi-Homing Using per-network Authoritative Edge Device Synchronization - In some embodiments, edge devices associated with a network segment are identified. One of the devices is elected as an authoritative device and any previous authoritative devices are instructed to halt forwarding network traffic to an overlay network. | 04-24-2014 |
Sitarama Narayana Bulusu, Hyderabad IN
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20130060820 | Data Masking Setup - Methods and systems for masking data columns in a database are described herein. The method describes obtaining a masking template. Further the method describes associating the masking template with at least one rule and selecting columns based on the at least one rule. The method further describes identifying at least one column from the selected columns for applying masking setup and initiating masking setup on the at least one column based on the masking template. | 03-07-2013 |
Venkata Bulusu, Bangalore IN
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20080320552 | ARCHITECTURE AND SYSTEM FOR ENTERPRISE THREAT MANAGEMENT - Enterprise threat assessment and management provides both physical and logical security. Physical access control systems are configured to identify physical events in the physical domain, and logical access control systems are configured to identify logical events in the logical domain. Connectors establish uninterrupted coupling to the physical and logical access control systems. Event middleware is configured to selectively subscribe only to those events that correspond to defined policies. The policies define a correlation of the physical and logical events, actions are initiated depending upon the correlated physical and logical events defined by the policies. | 12-25-2008 |