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Bulusu
Atchyuta Rama Chandra Murty Bulusu, Perchtoldsdorf AT
| Patent application number | Description | Published |
|---|---|---|
| 20100035987 | PLEUROMUTILIN DERIVATIVES FOR THE TREATMENT OF DISEASES MEDIATED BY MICROBES - A pleuromutilin derivative compound of general formula (I) | 02-11-2010 |
| 20120029072 | PLEUROMUTILIN DERIVATIVES FOR THE TREATMENT OF DISEASES MEDIATED BY MICROBES - Disclosed are pleuromutilin derivatives of formula (I) | 02-02-2012 |
Bhanu Teja Bulusu, Hyderabad IN
| Patent application number | Description | Published |
|---|---|---|
| 20080286373 | Ziprasidone formulations - A ziprasidone formulation containing at least (a) one ziprasidone compound and at least an excipient component (b) that includes at least one of | 11-20-2008 |
| 20080319048 | Solubilized formulation of docetaxel without tween 80 - Lyophilizates containing docetaxel and the use thereof in preparing concentrated liquid formulations, and ready to use formulations for injection, as well as such concentrates and ready to use formulations themselves are disclosed in which Tween surfactants are avoided so that hypersensitivity reactions to Tween surfactants can be avoided and docetaxel can be administered at higher doses and/or for longer periods of time and/or for additional treatment cycles. | 12-25-2008 |
Chandra Sekhar Veera Venkata Naga Bulusu, Hyderabad IN
| Patent application number | Description | Published |
|---|---|---|
| 20090263475 | DEXLANSOPRAZOLE COMPOSITIONS - Premixes of dexlansoprazole with pharmaceutical excipients, processes for preparing premixes, pharmaceutical formulations containing the premixes, and their use in treatment of erosive esophagitis and heartburn associated with non-erosive gastroesophageal reflux disease. | 10-22-2009 |
Gopi Kumar Bulusu, Vasakhapatnam IN
| Patent application number | Description | Published |
|---|---|---|
| 20110023008 | METHOD FOR OPTIMIZING AN ARCHITECTURAL MODEL OF A MICROPROCESSOR - A method for optimizing an architectural model of a microprocessor includes representing an instruction set of the microprocessor as a graph by configuring the elements of the instruction set as nodes of the graph. Determination is made whether the nodes with identical bit position and value encoding is present in the graph. If the nodes with the identical bit position and value encoding are present, a path from a source node to a target node is separated into a common node for each node in the graph. The common node is reused to optimize common paths out of the graph and the source node is directly connected to the common node in the graph using a forward edge. A back-edge is added from the common node to the source node through the target node and the above steps are recursively repeated until all the nodes of the graph are processed. | 01-27-2011 |
Gopi Kumar Bulusu, Tamil Nadu IN
| Patent application number | Description | Published |
|---|---|---|
| 20090199089 | Converting a Heterogeneous Document - A method for transforming a heterogeneous compound document to a desired format based on a prescribed model is provided. The method comprises the steps of: (i) specifying the components of the heterogeneous compound document as a hierarchical tree structure in multiple formats and specifying the input sources of information for each of the components as part of the model; verifying and composing the heterogeneous compound document using a modeling language parser and a document composer by dynamically obtaining input information from the sources specified in the model and (iii) converting the input compound document to the desired format using the document composer. A system for performing the abovementioned method is also provided. | 08-06-2009 |
Millik Bulusu, Olympia, WA US
| Patent application number | Description | Published |
|---|---|---|
| 20120079259 | METHOD TO ENSURE PLATFORM SILICON CONFIGURATION INTEGRITY - Some aspects include beginning a power on self test (POST) by a BIOS for a computer system; enumerating the computer system by the BIOS; providing, based on the enumeration of the computer system by the BIOS, at least one configuration setting of the computer system to a management engine (ME) of the computer system; and applying a lock to the at least one configuration setting by the ME to manage a change to the at least one configuration setting, all prior to an ending of the POST. | 03-29-2012 |
Ravi Bulusu, Santa Clara, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100104008 | METHOD AND SYSTEM FOR PERFORMING TWO-DIMENSIONAL TRANSFORM ON DATA VALUE ARRAY WITH REDUCED POWER CONSUMPTION - A method and system for performing a 2D transform is disclosed. The 2D transform may include a row transform and/or a column transform. When performing the row or column transform, it may be determined whether each of different subsets of the data values including a partition of a row or column includes at least one zero value, whether each of different subsets of a first subset of the partition includes at least one zero value, and whether each of different subsets of at least one other subset of the partition includes at least one zero value. When performing the row or column transform, at least one transformation operation on at least one zero value may be bypassed or performed in a reduced-power manner, where such transformation operation would otherwise be performed in a manner consuming full power if the zero value were a non-zero value. | 04-29-2010 |
Ravi Bulusu, San Jose, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090259862 | CLOCK-GATED SERIES-COUPLED DATA PROCESSING MODULES - A clock module is coupled in parallel to a number of data processing modules that are coupled in series. The data processing modules can be individually clock-gated. Each of the data processing modules can determine whether or not it can be placed into an idle state. To reduce power consumption, any subset of the data processing modules that are eligible to be placed in an idle state can be clock-gated. The remaining data processing modules can continue to receive clock signals from the clock module and thus can continue to process data. | 10-15-2009 |
Shekher Bulusu, Fremont, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110131302 | MINIMUM DISRUPTION MST RECONFIGURATION (MDMR) - In one embodiment, a first multiple spanning tree (MST) region configuration for an MST process may be maintained at a switch in a computer network, where the first configuration has a virtual local area network (VLAN)-to-instance (VI) mapping that maps each of one or more VLANs to one of one or more MST instances in the MST region. The switch may subsequently receive a second MST region configuration that has a different VI mapping than the first configuration, and may determine one or more VLANs of the second configuration that have a different VI mapping from the first configuration (“affected VLANs”). Accordingly, in response to a trigger to apply the second configuration at the switch, the affected VLANs are blocked for a delay, and the second configuration may be applied at the switch without restarting the MST process. | 06-02-2011 |
| 20110261724 | SHARED VIRTUAL DEVICE PORTS - In one embodiment, a solution is provided wherein multiple virtual devices may be configured on the same physical port of a network device. For example, a first virtual device and a second virtual device may be configured to use the same physical port. A single internal spanning tree instance may be configured for both the first virtual device and the second virtual device. | 10-27-2011 |
Venkata Bulusu, Bangalore IN
| Patent application number | Description | Published |
|---|---|---|
| 20080320552 | ARCHITECTURE AND SYSTEM FOR ENTERPRISE THREAT MANAGEMENT - Enterprise threat assessment and management provides both physical and logical security. Physical access control systems are configured to identify physical events in the physical domain, and logical access control systems are configured to identify logical events in the logical domain. Connectors establish uninterrupted coupling to the physical and logical access control systems. Event middleware is configured to selectively subscribe only to those events that correspond to defined policies. The policies define a correlation of the physical and logical events, actions are initiated depending upon the correlated physical and logical events defined by the policies. | 12-25-2008 |